Fixed State Machine

/*
 * Finite state machine.
 * If input 'a' is asserted, the state machine
 * moves IDLE->STATE_1->FINAL and remains in FINAL.
 * If 'a' is not asserted, FSM returns to idle.
 * Output 'out1' asserts when state machine is in
 * STATE_1. 'out2' asserts when state machine is in
 * FINAL state.
 */
module fsm (
  input  logic clk ,
  input  logic rst ,
  input  logic a   ,
  output logic out1,
  output logic out2
);

  enum {
    IDLE,    // Waiting for the sun to rise
    STATE_1, // Doing a lot of work here!
    FINAL,   // Whew, done, lets go back to Idle
    XXX      // Trap!
  } state;

  // State transitions
  always @(posedge clk or posedge rst) begin
    if (rst)
      state <= IDLE;
    else
      case (state)
        IDLE:
          if (a) state <= STATE_1;
          else   state <= IDLE;

        STATE_1:
          if (a) state <= FINAL;
          else   state <= IDLE;

        FINAL:
          if (a) state <= FINAL;
          else   state <= IDLE;

        default:
          state <= XXX;
      endcase
  end

  // State machine output
  assign out1 = (state == STATE_1);
  assign out2 = (state == FINAL);

endmodule