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vrangan

Fixed State Machine

Jul 3rd, 2022
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  1. /*
  2.  * Finite state machine.
  3.  * If input 'a' is asserted, the state machine
  4.  * moves IDLE->STATE_1->FINAL and remains in FINAL.
  5.  * If 'a' is not asserted, FSM returns to idle.
  6.  * Output 'out1' asserts when state machine is in
  7.  * STATE_1. 'out2' asserts when state machine is in
  8.  * FINAL state.
  9.  */
  10. module fsm (
  11.   input  logic clk ,
  12.   input  logic rst ,
  13.   input  logic a   ,
  14.   output logic out1,
  15.   output logic out2
  16. );
  17.  
  18.   enum {
  19.     IDLE,    // Waiting for the sun to rise
  20.     STATE_1, // Doing a lot of work here!
  21.     FINAL,   // Whew, done, lets go back to Idle
  22.     XXX      // Trap!
  23.   } state;
  24.  
  25.   // State transitions
  26.   always @(posedge clk or posedge rst) begin
  27.     if (rst)
  28.       state <= IDLE;
  29.     else
  30.       case (state)
  31.         IDLE:
  32.           if (a) state <= STATE_1;
  33.           else   state <= IDLE;
  34.  
  35.         STATE_1:
  36.           if (a) state <= FINAL;
  37.           else   state <= IDLE;
  38.        
  39.         FINAL:
  40.           if (a) state <= FINAL;
  41.           else   state <= IDLE;
  42.  
  43.         default:
  44.           state <= XXX;
  45.       endcase
  46.   end
  47.    
  48.   // State machine output
  49.   assign out1 = (state == STATE_1);
  50.   assign out2 = (state == FINAL);
  51.  
  52. endmodule
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