RAM VERILOG

module and2(output c, input a, input b);

wire w;
nand mynand(w,a,b);
nand mynand2(c,w);

endmodule


module or2(output c, input a, input b);

wire a1, b1;

nand not1(a1, a);
nand not2(b1, b);
nand mynand(c, a1, b1);

endmodule

module mux21(output o, input s, i0, i1);

wire s1, a1, a2;
nand not1(s1, s);
and2 and_1(a1, s1, i0);
and2 and_2(a2, s, i1);
or2 or_1(o, a1, a2);

endmodule

module dlatch(output q, q0, input d, clock);

wire s,r,s0,r_;
and2 myand(s,d,d);
nand not1(r,d);
nand(s0, clock, s);
nand(r_,clock,r);
nand(q,s0,q0);
nand(q0,r_,q);

endmodule

module dff_rising(output q, q0, input d, clock);

wire clock0, Q,Q0;
nand not1(clock0,clock);
dlatch d1(Q,Q0,d,clock0);
dlatch d2(q,q0,Q,clock);

endmodule

module binary_cell(output out, input in, input load, input clock);

wire w1,w2;
mux21 mux(w1, load, out,in);
dff_rising dff(out, w2, w1, clock);

endmodule

module demux21(output o0, o1, input s, in);

wire w;

nand mynand(w, s);
and2 myand1(o0, w, in);
and2 myand2(o1, s, in);

endmodule

module demux41(output [3:0] o, input [1:0] s, input in, e);

wire o0, o1;
wire [3:0] o2;

demux21 d4_1(o0, o1, s[1], in);
demux21 d4_2(o2[0], o2[1], s[0], o0);
demux21 d4_3(o2[2], o2[3], s[0], o1);
and2 myand [3:0] (o, o2, e);

endmodule



module mux16(output [15:0] o, input s, input [15:0] i0, i1);

wire w;
wire [15:0] a1, a2;

nand(w, s);
and2 myand [15:0] (a1, w, i0);
and2 myand1 [15:0] (a2, s, i1);
or2 myor1 [15:0] (o, a1, a2);

endmodule

module mux4(output [15:0] o, input [1:0] s, input [15:0] i0, i1, i2, i3);

wire [15:0]o1, o2;
mux16 m1(o1, s[0], i0, i1);
mux16 m2(o2, s[0], i2, i3);
mux16 m3(o, s[1], o1, o2);

endmodule

module mux8(output [15:0] o, input [2:0] s, input [15:0] i0, i1, i2, i3, i4, i5, i6, i7);

wire [15:0] o1, o2;

mux4 m1(o1, s[1:0], i0, i1, i2, i3);
mux4 m2(o2, s[1:0], i4, i5, i6, i7);
mux16 m3(o, s[2], o1, o2);

endmodule

module demux81(output [7:0] o, input [2:0] s, input in);

wire w;
nand mynand(w, s[2]);
demux41 d1(o[3:0], s[1:0], in, w);
demux41 d2(o[7:4], s[1:0], in, s[2]);

endmodule

module reg_16bit(output [15:0] out, input [15:0] in, input load, input clock);

binary_cell mycell[15:0](out,in,load,clock);

endmodule

module ram_8(output [15:0] out, input [2:0] address,input [15:0] in, input load, input clock);

wire [7:0] l;
wire [15:0] o0, o1, o2,o3,o4,o5,o6,o7;

demux81 d1(l,address,load);

reg_16bit reg0(o0, in, l[0], clock);
reg_16bit reg1(o1, in, l[1], clock);
reg_16bit reg2(o2, in, l[2], clock);
reg_16bit reg3(o3, in, l[3], clock);
reg_16bit reg4(o4, in, l[4], clock);
reg_16bit reg5(o5, in, l[5], clock);
reg_16bit reg6(o6, in, l[6], clock);
reg_16bit reg7(o7, in, l[7], clock);

mux8 m1(out, address, o0,o1,o2,o3,o4,o5,o6,o7);

endmodule

module ram_64(output [15:0] out, input [5:0] address, input [15:0] in, input load, input clock);

wire [7:0] l;
wire [15:0] o0, o1, o2 ,o3 ,o4, o5, o6, o7;

demux81 d1(l, address[5:3], load);

ram_8 r0(o0, address[2:0], in, l[0], clock);
ram_8 r1(o1, address[2:0], in, l[1], clock);
ram_8 r2(o2, address[2:0], in, l[2], clock);
ram_8 r3(o3, address[2:0], in, l[3], clock);
ram_8 r4(o4, address[2:0], in, l[4], clock);
ram_8 r5(o5, address[2:0], in, l[5], clock);
ram_8 r6(o6, address[2:0], in, l[6], clock);
ram_8 r7(o7, address[2:0], in, l[7], clock);

mux8 m1(out, address[5:3], o0,o1,o2,o3,o4,o5,o6,o7);

endmodule

module ram_512(output [15:0] out, input [8:0] address, input [15:0] in, input load, input clock);

wire [7:0] l;
wire [15:0] o0, o1, o2 ,o3 ,o4, o5, o6, o7;

demux81 d1(l,address[8:6],load);

ram_64 r0(o0, address[5:0], in, l[0], clock);
ram_64 r1(o1, address[5:0], in, l[1], clock);
ram_64 r2(o2, address[5:0], in, l[2], clock);
ram_64 r3(o3, address[5:0], in, l[3], clock);
ram_64 r4(o4, address[5:0], in, l[4], clock);
ram_64 r5(o5, address[5:0], in, l[5], clock);
ram_64 r6(o6, address[5:0], in, l[6], clock);
ram_64 r7(o7, address[5:0], in, l[7], clock);

mux8 m1(out,address[8:6], o0,o1,o2,o3,o4,o5,o6,o7);

endmodule

module ram_4k(output [15:0] out, input [11:0] address, input [15:0] in, input load, input clock);

wire [7:0] l;
wire [15:0] o0, o1, o2 ,o3 ,o4, o5, o6, o7;

demux81 d1(l,address[11:9],load);

ram_512 r0(o0, address[8:0], in, l[0], clock);
ram_512 r1(o1, address[8:0], in, l[1], clock);
ram_512 r2(o2, address[8:0], in, l[2], clock);
ram_512 r3(o3, address[8:0], in, l[3], clock);
ram_512 r4(o4, address[8:0], in, l[4], clock);
ram_512 r5(o5, address[8:0], in, l[5], clock);
ram_512 r6(o6, address[8:0], in, l[6], clock);
ram_512 r7(o7, address[8:0], in, l[7], clock);

mux8 m1(out, address[11:9], o0,o1,o2,o3,o4,o5,o6,o7);

endmodule

module ram_16k(output [15:0] out, input [14:0] address, input [15:0] in, input load, input clock);

wire [7:0] l;
wire [15:0] o0, o1, o2 ,o3 ,o4, o5, o6, o7;

demux81 d1(l,address[14:12],load);

ram_4k r0(o0, address[11:0], in, l[0], clock);
ram_4k r1(o1, address[11:0], in, l[1], clock);
ram_4k r2(o2, address[11:0], in, l[2], clock);
ram_4k r3(o3, address[11:0], in, l[3], clock);
ram_4k r4(o4, address[11:0], in, l[4], clock);
ram_4k r5(o5, address[11:0], in, l[5], clock);
ram_4k r6(o6, address[11:0], in, l[6], clock);
ram_4k r7(o7, address[11:0], in, l[7], clock);

mux8 m1(out, address[14:12], o0,o1,o2,o3,o4,o5,o6,o7);

endmodule