;Tabla ASCII:
; https://fsymbols.com/images/ascii.png


.EQU Clock = 16000000 ;processor’s clock frequency, Hz
.EQU Baud = 9600 ;desired serial port baud rate (bits per second)
.EQU UBRRvalue = Clock/(Baud*16) -1 ;calculates value to be put in UBRR0H:L

ldi r16, 0b11111111
out ddrb, r16
RCALL config_ADC ;Configurar el conversor ADC
rcall init_USART0
conv:
    LDS r17, ADCSRA
    ORI r17, (1<< ADSC)
    STS ADCSRA, r17         ;Disparo la conversion AC to Digital
    bit:
        LDS r20, ADCSRA
        SBRC r20, ADSC      ;Espero que termine la conversion.
        rjmp bit
    LDS r21, ADCH           ;Leo el valor de la conversion.
    STS UDR0, r21  ;transmits the [modified] byte
    rcall delay100ms
    if:
        cpi r21, 140
        brlo conv
    then:
        ldi r16, 0xff
        out portb, r16
        rcall delay100ms
        ldi r16, 0x00
        out portb, r16

    rcall delay1s

rjmp conv


config_ADC:
    push r16
    LDI R16, (1<<ADEN)
    ;ADC Enable
    ORI R16, (0<<ADATE)
    ;ADC Auto Trigger Enable
    ORI R16, (1<<ADPS2) | (1<<ADPS1) | (1<<ADPS0)
    ;ADPSx=3: ADC Prescaler Select Bits (ADPS2:0=111 -> 128)
    STS ADCSRA, R16
    ;_> ADOSRA: The ADC Control and Status register A
    LDI R16, (0<<ADTS2) | (0<<ADTS1) | (1<<ADTS0)
    ;ADTSx-1: trigger source Analog Comparator
    STS ADCSRB, R16
    ;-> ADCSRB: The ADC Control and Status register B
    LDI R16, (2<<MUX0)
    ;MUXx-1: input channel 1: MUX5:0-00001
    ORI R16, (0<<REFS1) | (1<<REFS0)
    ;AREF-1: internal 5V reference (REF$1:0-01)
    ORI R16, (1<<ADLAR)
    ;ADC 8 bits resolution
    STS ADMUX, R16
    ; -> ADMUX: The ADC multiplexer Selection Register
    LDI R16, (1<<ADC1D)
    ;ADC disable digital input circuitry for channel 1 (saves energy)
    STS DIDR0, R16
    ; -> DIDRO: Digital Input Disable Register
    LDI R16, (0<<PRADC)
    ;ADC disable the power reduction saving for the ADC circuitry (not necesary)
    STS PRR, R16
    ;-> PRR: Power Reduction Register
    pop r16
RET

;------- initialize USART0 as 9600baud, asynchronous, 8 data bits, 1 stop bit, no parity -----
init_USART0:
    PUSH R16
    LDI R16, LOW(UBRRvalue)
    STS UBRR0L, R16   ;load the low byte
    LDI R16, HIGH(UBRRvalue)
    STS UBRR0H, R16   ;load the low byte
    ; enable receive and transmit, enable USART0 interrupts (UDR empty, Tx finished, Rx finished)
    LDI R16, (0<<RXEN0)|(1<<TXEN0)|(0<<UDRIE0)|(0<<TXCIE0)|(0<<RXCIE0)
    STS UCSR0B, R16 ;set control register UCSR0B with the corresponding bits
    ; configure USART 0 as asynchronous, set frame format: 8 data bits, 1 stop bit, no parity
    LDI R16, (0<<UMSEL00) |(1<<UCSZ01)|(1<<UCSZ00) |(0<<USBS0)|(0<<UPM01)|(0<<UPM00)
    STS UCSR0C, R16 ;set control register UCSR0C with the corresponding bits
    POP R16
    RET

delay1s:
; 1s at 16.0 MHz
    push r18
    push r19
    push r20
    ldi  r18, 82
    ldi  r19, 43
    ldi  r20, 0
L1s: dec  r20
    brne L1s
    dec  r19
    brne L1s
    dec  r18
    brne L1s
    lpm
    pop r20
    pop r19
    pop r18
    nop
ret

delay100ms:
; 1s at 16.0 MHz
    push r18
    push r19
    push r20
    ldi  r18, 9
    ldi  r19, 30
    ldi  r20, 229
L100ms: dec  r20
    brne L100ms
    dec  r19
    brne L100ms
    dec  r18
    brne L100ms
    nop
    pop r20
    pop r19
    pop r18
    nop
ret