/*************************************************************************************************************
 *
 *     Project: ROPA
 *    Language: C
 *      Module: firmware
 *     Initial: 2018-01-11
 *      Author: C.Schoenegger
 *   Copyright: illumination network systems GmbH
 *
 * Description: ADC trigger via TPM, sampling of several signals, and eDMA transfers into ping-pong buffer.
 *
 *************************************************************************************************************/
#include "adc_task.h"

/* FreeRTOS kernel includes */
#include "FreeRTOS.h"
#include "queue.h"
#include "task.h"
#include "timers.h"

/* drivers */
#include "error_codes.h"
#include "fsl_adc16.h"
#include "fsl_debug_console.h"
#include "fsl_dmamux.h"
#include "fsl_edma.h"
#include "fsl_tpm.h"
#include "rtos_config.h"

#include <cr_section_macros.h>

/*************************************************************************************************************
 * Definitions
 *************************************************************************************************************/
/*! @brief Signal to ADC channel assignment */
enum adc_channel_t
{
	ADC0_CHANNEL_I1 = 10U,		//!< I1 signal connected to this channel on ADC0
	ADC0_CHANNEL_Q1,      		//!< Q1 signal connected to this channel on ADC0
	ADC1_CHANNEL_I2 = 10U,		//!< I2 signal connected to this channel on ADC1
	ADC1_CHANNEL_Q2       		//!< Q2 signal connected to this channel on ADC1
};

/*! @brief ADC to eDMA channel assignment */
enum dma_source_t
{
	ADC0_CHANNEL10_EDMA0 = 0U,	//!< ADC0 channel 10 connected to EDMA channel 0
	ADC0_CHANNEL11_EDMA1,     	//!< ADC0 channel 11 connected to EDMA channel 1
	ADC1_CHANNEL10_EDMA2,     	//!< ADC1 channel 10 connected to EDMA channel 2
	ADC1_CHANNEL11_EDMA3      	//!< ADC1 channel 11 connected to EDMA channel 3
};

/*************************************************************************************************************
 * Variables
 *************************************************************************************************************/
/*! @brief ADC queue which tells the buffer switch events */
QueueHandle_t g_adcQueue;

/*! @brief ADC ping-pong buffer for each signal -> organized as nested array */
/** @cond */__BSS(RAM2) /** @endcond */ uint16_t g_adcValues[NUM_ADC_SIGNALS][2U*ADC_BUFFER_SIZE];

//TickType_t g_ticks1;
//TickType_t g_ticks2;

/*! @brief ADC task handle used for suspend/resume operations */
static TaskHandle_t g_adcTaskHandle;

/*! @brief DMA handles for each channel */
static edma_handle_t g_edmaHandle[NUM_ADC_SIGNALS];

/*! @brief DMA channel transfer completion flag */
static volatile bool g_edmaTransferDone[NUM_ADC_SIGNALS];

/*************************************************************************************************************
 * Functions
 *************************************************************************************************************/
/**
 * @brief EDMA interrupt callback
 *
 * The EDMA interrupt is configured to fire twice per buffer and channel (kEDMA_HalfInterruptEnable).
 *
 * @param handle ignored in this function, the handles are saved in g_edmaHandle
 * @param userData the DMA source is contained as user data (configured at EDMA_SetCallback() below)
 * @param transferDone ignored in this function
 * @param tcds ignored in this function
 */
static void EDMA_Callback(edma_handle_t *handle, void *userData, bool transferDone, uint32_t tcds)
{
	enum dma_source_t source = (enum dma_source_t) userData;

	/* Set unused arguments */
	(void) handle;
	(void) transferDone;
	(void) tcds;

	/* Clear Edma interrupt flags and set Transfer-Done flags */
	switch(source)
	{
		case ADC0_CHANNEL10_EDMA0:
			EDMA_ClearChannelStatusFlags(DMA0, ADC0_CHANNEL10_EDMA0, kEDMA_InterruptFlag);
			g_edmaTransferDone[ADC0_CHANNEL10_EDMA0] = true;
			break;
		case ADC0_CHANNEL11_EDMA1:
			EDMA_ClearChannelStatusFlags(DMA0, ADC0_CHANNEL11_EDMA1, kEDMA_InterruptFlag);
			g_edmaTransferDone[ADC0_CHANNEL11_EDMA1] = true;
			break;
		case ADC1_CHANNEL10_EDMA2:
			EDMA_ClearChannelStatusFlags(DMA0, ADC1_CHANNEL10_EDMA2, kEDMA_InterruptFlag);
			g_edmaTransferDone[ADC1_CHANNEL10_EDMA2] = true;
			break;
		case ADC1_CHANNEL11_EDMA3:
			EDMA_ClearChannelStatusFlags(DMA0, ADC1_CHANNEL11_EDMA3, kEDMA_InterruptFlag);
			g_edmaTransferDone[ADC1_CHANNEL11_EDMA3] = true;
			break;
		default:
			break;
	}
}

/**
 * @brief ADC FreeRTOS task
 *
 *  This task waits until a transfer-done event is signaled by the DMA ISR and tells a buffer
 *  switch event using the ADC message queue. The ADC message queue is used to serialize the
 *  various DMA events that run in parallel.
 *
 *  @param arg not used by this function
 */
static void ADC_Task(void *arg)
{
	uint8_t adcBufferSwitch[NUM_ADC_SIGNALS];

	enum buffer_state_t bufferSelect = BUFFERS_NOT_READY;

	/* Set unused argument */
	(void) arg;

	PRINTF("ADC Task started!\r\n");

	//g_ticks1 = xTaskGetTickCount();
	//PRINTF("start ticks: %d\r\n", xTaskGetTickCount());

	/* Buffer and variable initialization */
	memset(g_adcValues[ADC0_CHANNEL10_EDMA0], 0U, sizeof(g_adcValues[ADC0_CHANNEL10_EDMA0]));
	memset(g_adcValues[ADC0_CHANNEL11_EDMA1], 0U, sizeof(g_adcValues[ADC0_CHANNEL11_EDMA1]));
	memset(g_adcValues[ADC1_CHANNEL10_EDMA2], 0U, sizeof(g_adcValues[ADC1_CHANNEL10_EDMA2]));
	memset(g_adcValues[ADC1_CHANNEL11_EDMA3], 0U, sizeof(g_adcValues[ADC1_CHANNEL11_EDMA3]));

	g_edmaTransferDone[ADC0_CHANNEL10_EDMA0] = false;
	g_edmaTransferDone[ADC0_CHANNEL11_EDMA1] = false;
	g_edmaTransferDone[ADC1_CHANNEL10_EDMA2] = false;
	g_edmaTransferDone[ADC1_CHANNEL11_EDMA3] = false;

	adcBufferSwitch[ADC0_CHANNEL10_EDMA0] = 0U;
	adcBufferSwitch[ADC0_CHANNEL11_EDMA1] = 0U;
	adcBufferSwitch[ADC1_CHANNEL10_EDMA2] = 0U;
	adcBufferSwitch[ADC1_CHANNEL11_EDMA3] = 0U;

	/* suspend and wait on external ADC enable signal */
	vTaskSuspend(NULL);

	while(1)
	{
		if(g_edmaTransferDone[ADC0_CHANNEL10_EDMA0] == true)
		{
			g_edmaTransferDone[ADC0_CHANNEL10_EDMA0] = false;
			bufferSelect = (adcBufferSwitch[ADC0_CHANNEL10_EDMA0] == 0U) ? I1_LOWER_READY : I1_UPPER_READY;
			adcBufferSwitch[ADC0_CHANNEL10_EDMA0] = 1U - adcBufferSwitch[ADC0_CHANNEL10_EDMA0];
		}
		else if(g_edmaTransferDone[ADC0_CHANNEL11_EDMA1] == true)
		{
			g_edmaTransferDone[ADC0_CHANNEL11_EDMA1] = false;
			bufferSelect = (adcBufferSwitch[ADC0_CHANNEL11_EDMA1] == 0U) ? Q1_LOWER_READY : Q1_UPPER_READY;
			adcBufferSwitch[ADC0_CHANNEL11_EDMA1] = 1U - adcBufferSwitch[ADC0_CHANNEL11_EDMA1];
		}
		else if(g_edmaTransferDone[ADC1_CHANNEL10_EDMA2] == true)
		{
			g_edmaTransferDone[ADC1_CHANNEL10_EDMA2] = false;
			bufferSelect = (adcBufferSwitch[ADC1_CHANNEL10_EDMA2] == 0U) ? I2_LOWER_READY : I2_UPPER_READY;
			adcBufferSwitch[ADC1_CHANNEL10_EDMA2] = 1U - adcBufferSwitch[ADC1_CHANNEL10_EDMA2];
		}
		else if(g_edmaTransferDone[ADC1_CHANNEL11_EDMA3] == true)
		{
			g_edmaTransferDone[ADC1_CHANNEL11_EDMA3] = false;
			bufferSelect = (adcBufferSwitch[ADC1_CHANNEL11_EDMA3] == 0U) ? Q2_LOWER_READY : Q2_UPPER_READY;
			adcBufferSwitch[ADC1_CHANNEL11_EDMA3] = 1U - adcBufferSwitch[ADC1_CHANNEL11_EDMA3];
		}

		/* send the buffer complete events via message queue */
		if(bufferSelect != BUFFERS_NOT_READY)
		{
			if(xQueueSend(g_adcQueue, &bufferSelect, 0U) != pdPASS)
			{
				throwError(ERROR_MESSAGE_QUEUE_FULL);
				PRINTF("%s\r\n", getErrorMessage(ERROR_MESSAGE_QUEUE_FULL));
			}
			bufferSelect = BUFFERS_NOT_READY;
		}
	}
}

/**
 * @brief TPM configuration used to assert the hardware trigger lines of both ADC interfaces
 *
 * Configuration for a free-running counter that triggers SC1A at counter == 0 and SC1B
 * at counter == half period. The period is currently set to 8 us to achieve a sampling
 * rate of 125 kHz. The 12 MHz oscillator clock is used to generate the counter events.
 */
static void TPM_Configuration(void)
{
	tpm_config_t tpmConfig;

	/* set OSCERCLK as TPM input clock source */
	CLOCK_SetTpmClock(2U);

	TPM_GetDefaultConfig(&tpmConfig);

	TPM_Init(TPM1, &tpmConfig);
	TPM_Init(TPM2, &tpmConfig);

	/* Set the timer to be in free-running mode */
	TPM_SetTimerPeriod(TPM1, USEC_TO_COUNT(8U, CLOCK_GetFreq(kCLOCK_Osc0ErClkUndiv)));
	TPM_SetTimerPeriod(TPM2, USEC_TO_COUNT(8U, CLOCK_GetFreq(kCLOCK_Osc0ErClkUndiv)));

	/* Setup the output compare mode to pulse on a match */
	TPM_SetupOutputCompare(TPM1, kTPM_Chnl_0, kTPM_HighPulseOutput, 0U);
	TPM_SetupOutputCompare(TPM1, kTPM_Chnl_1, kTPM_HighPulseOutput, USEC_TO_COUNT(4U, CLOCK_GetFreq(kCLOCK_Osc0ErClkUndiv)));

	TPM_SetupOutputCompare(TPM2, kTPM_Chnl_0, kTPM_HighPulseOutput, 0U);
	TPM_SetupOutputCompare(TPM2, kTPM_Chnl_1, kTPM_HighPulseOutput, USEC_TO_COUNT(4U, CLOCK_GetFreq(kCLOCK_Osc0ErClkUndiv)));

	/* Enable DMA */
	TPM1->CONTROLS[kTPM_Chnl_0].CnSC |= TPM_CnSC_DMA_MASK;
	TPM1->CONTROLS[kTPM_Chnl_1].CnSC |= TPM_CnSC_DMA_MASK;
	TPM2->CONTROLS[kTPM_Chnl_0].CnSC |= TPM_CnSC_DMA_MASK;
	TPM2->CONTROLS[kTPM_Chnl_1].CnSC |= TPM_CnSC_DMA_MASK;
}

/**
 * @brief Configuration of ADC0 and ADC1 interfaces
 *
 * The 12 MHz oscillator is used as clock source for the ADC module. The conversion time
 * of both ADC interfaces is set to 24 ADCK cycles which results in a conversion rate of
 * 500 kHz, fast enough to sample two channels at 125 kHz sampling rate.
 * The ADC resolution is set to 12 bit.
 * Hardware triggering is enabled via TPM channel pulses.
 * Auto-Calibration is performed once at initialization.
 */
static void ADC16_Configuration(void)
{
    adc16_config_t adcConfig;
    adc16_channel_config_t adcChannelConfig;

    /*
    * Initialization ADC for 12bit resolution, alternate crystal clock, long sample and high speed mode
    */
    ADC16_GetDefaultConfig(&adcConfig);

    adcConfig.clockDivider = kADC16_ClockDivider1;			// divide by 1, resulting ADCK = 12 MHz
    adcConfig.clockSource = kADC16_ClockSourceAlt2;			// clock source is the alternate (quartz) clock (12 MHz)
    adcConfig.enableHighSpeed = true;						// high freqeuency clock mode -> 2 extra ADCK cycles
    adcConfig.longSampleMode = kADC16_LongSampleCycle6;		// long sample mode with 2 extra ADCK cycles
    adcConfig.resolution = kADC16_ResolutionSE12Bit;		// 12 bit resolution -> 20 ADCK cycles
    adcConfig.enableContinuousConversion = false;			// single conversion mode

    ADC16_Init(ADC0, &adcConfig);
    ADC16_Init(ADC1, &adcConfig);

#if defined(FSL_FEATURE_ADC16_HAS_CALIBRATION) && FSL_FEATURE_ADC16_HAS_CALIBRATION
    /* Auto calibration */
    if (kStatus_Success == ADC16_DoAutoCalibration(ADC0))
    {
    	PRINTF("ADC0 Auto-Calibration Done!\r\n");
    }
    else
    {
    	throwError(ERROR_ADC_AUTOCALIBRATION_FAILED);
		PRINTF("%s\r\n", getErrorMessage(ERROR_ADC_AUTOCALIBRATION_FAILED));
    }
    if (kStatus_Success == ADC16_DoAutoCalibration(ADC1))
	{
    	PRINTF("ADC1 Auto-Calibration Done!\r\n");
	}
	else
	{
		throwError(ERROR_ADC_AUTOCALIBRATION_FAILED);
		PRINTF("%s\r\n", getErrorMessage(ERROR_ADC_AUTOCALIBRATION_FAILED));
	}
#endif

    /* Enable hardware trigger for both ADC0 and ADC1.  */
    ADC16_EnableHardwareTrigger(ADC0, true);
    ADC16_EnableHardwareTrigger(ADC1, true);

    /* Channel Configuration */
	adcChannelConfig.enableDifferentialConversion = false;				// configured for single-ended conversion
	adcChannelConfig.enableInterruptOnConversionCompleted = false;		// disable interrupt on conversion completion

	/* Configure SC1A and SC1B registers for ADC0 and ADC1 */
	adcChannelConfig.channelNumber = ADC0_CHANNEL_I1;
	ADC16_SetChannelConfig(ADC0, 0U, &adcChannelConfig);

	adcChannelConfig.channelNumber = ADC0_CHANNEL_Q1;
	ADC16_SetChannelConfig(ADC0, 1U, &adcChannelConfig);

	adcChannelConfig.channelNumber = ADC1_CHANNEL_I2;
	ADC16_SetChannelConfig(ADC1, 0U, &adcChannelConfig);

	adcChannelConfig.channelNumber = ADC1_CHANNEL_Q2;
	ADC16_SetChannelConfig(ADC1, 1U, &adcChannelConfig);
}

/**
 * @brief Configuration of DMAMUX element
 *
 * The DMAMUX component uses the ADC-to-eDMA channel assignment defined above.
 */
static void DMAMUX_Configuration(void)
{
    /* Configure DMAMUX */
    DMAMUX_Init(DMAMUX0);

    DMAMUX_SetSource(DMAMUX0, ADC0_CHANNEL10_EDMA0, 28U); 	/* Map TPM1 channel 0 source to DMA channel 0 */
    DMAMUX_SetSource(DMAMUX0, ADC0_CHANNEL11_EDMA1, 29U); 	/* Map TPM1 channel 1 source to DMA channel 1 */
    DMAMUX_SetSource(DMAMUX0, ADC1_CHANNEL10_EDMA2, 30U); 	/* Map TPM2 channel 0 source to DMA channel 2 */
    DMAMUX_SetSource(DMAMUX0, ADC1_CHANNEL11_EDMA3, 31U); 	/* Map TPM2 channel 1 source to DMA channel 3 */

    /* Enable Channels in DMAMUX */
    DMAMUX_EnableChannel(DMAMUX0, ADC0_CHANNEL10_EDMA0);
    DMAMUX_EnableChannel(DMAMUX0, ADC0_CHANNEL11_EDMA1);
    DMAMUX_EnableChannel(DMAMUX0, ADC1_CHANNEL10_EDMA2);
    DMAMUX_EnableChannel(DMAMUX0, ADC1_CHANNEL11_EDMA3);
}

/**
 * @brief EDMA Configuration for continuous DMA transfers using double-buffering
 *
 * There is a problem in the fsl_edma driver which automatically stops every DMA
 * request after one transfer -> thus, the used TCD registers are written here and
 * configured for continuous DMA requests and to restart at the buffer start-addresses.
 * This permits minimal CPU interaction and the usage of enable/disable functions to
 * control the entire ADC sampling flow.
 */
static void EDMA_Configuration(void)
{
    edma_config_t edmaConfig;
    edma_transfer_config_t edmaTransferConfig;

    /* Initialize eDMA */
    EDMA_GetDefaultConfig(&edmaConfig);
    EDMA_Init(DMA0, &edmaConfig);

    EDMA_CreateHandle(&g_edmaHandle[ADC0_CHANNEL10_EDMA0], DMA0, ADC0_CHANNEL10_EDMA0);
    EDMA_CreateHandle(&g_edmaHandle[ADC0_CHANNEL11_EDMA1], DMA0, ADC0_CHANNEL11_EDMA1);
    EDMA_CreateHandle(&g_edmaHandle[ADC1_CHANNEL10_EDMA2], DMA0, ADC1_CHANNEL10_EDMA2);
    EDMA_CreateHandle(&g_edmaHandle[ADC1_CHANNEL11_EDMA3], DMA0, ADC1_CHANNEL11_EDMA3);

    EDMA_SetCallback(&g_edmaHandle[ADC0_CHANNEL10_EDMA0], EDMA_Callback, (void *) ADC0_CHANNEL10_EDMA0);
    EDMA_SetCallback(&g_edmaHandle[ADC0_CHANNEL11_EDMA1], EDMA_Callback, (void *) ADC0_CHANNEL11_EDMA1);
    EDMA_SetCallback(&g_edmaHandle[ADC1_CHANNEL10_EDMA2], EDMA_Callback, (void *) ADC1_CHANNEL10_EDMA2);
    EDMA_SetCallback(&g_edmaHandle[ADC1_CHANNEL11_EDMA3], EDMA_Callback, (void *) ADC1_CHANNEL11_EDMA3);

    /* Setup transfer configuration for ADC0 SC1A */
	EDMA_PrepareTransfer(&edmaTransferConfig, (void *)&ADC0->R[0U], sizeof(uint16_t),
						 (void *)g_adcValues[ADC0_CHANNEL10_EDMA0], sizeof(uint16_t), sizeof(uint16_t),
						 sizeof(g_adcValues[ADC0_CHANNEL10_EDMA0]), kEDMA_PeripheralToMemory);
	EDMA_SubmitTransfer(&g_edmaHandle[ADC0_CHANNEL10_EDMA0], &edmaTransferConfig);

	DMA0->TCD[ADC0_CHANNEL10_EDMA0].DLAST_SGA = -(2U*ADC_BUFFER_SIZE*sizeof(uint16_t));	// reset to start address
	DMA0->TCD[ADC0_CHANNEL10_EDMA0].CSR &= ~DMA_CSR_DREQ_MASK;							// don't disable DMA REQ line

	/* Setup transfer configuration for ADC0 SC1B */
	EDMA_PrepareTransfer(&edmaTransferConfig, (void *)&ADC0->R[1U], sizeof(uint16_t),
						 (void *)g_adcValues[ADC0_CHANNEL11_EDMA1], sizeof(uint16_t), sizeof(uint16_t),
						 sizeof(g_adcValues[ADC0_CHANNEL11_EDMA1]), kEDMA_PeripheralToMemory);
	EDMA_SubmitTransfer(&g_edmaHandle[ADC0_CHANNEL11_EDMA1], &edmaTransferConfig);

	DMA0->TCD[ADC0_CHANNEL11_EDMA1].DLAST_SGA = -(2U*ADC_BUFFER_SIZE*sizeof(uint16_t));	// reset to start address
	DMA0->TCD[ADC0_CHANNEL11_EDMA1].CSR &= ~DMA_CSR_DREQ_MASK;							// don't disable DMA REQ line

	/* Setup transfer configuration for ADC1 SC1A */
	EDMA_PrepareTransfer(&edmaTransferConfig, (void *)&ADC1->R[0U], sizeof(uint16_t),
						 (void *)g_adcValues[ADC1_CHANNEL10_EDMA2], sizeof(uint16_t), sizeof(uint16_t),
						 sizeof(g_adcValues[ADC1_CHANNEL10_EDMA2]), kEDMA_PeripheralToMemory);
	EDMA_SubmitTransfer(&g_edmaHandle[ADC1_CHANNEL10_EDMA2], &edmaTransferConfig);

	DMA0->TCD[ADC1_CHANNEL10_EDMA2].DLAST_SGA = -(2U*ADC_BUFFER_SIZE*sizeof(uint16_t));	// reset to start address
	DMA0->TCD[ADC1_CHANNEL10_EDMA2].CSR &= ~DMA_CSR_DREQ_MASK;							// don't disable DMA REQ line

	/* Setup transfer configuration for ADC1 SC1B */
	EDMA_PrepareTransfer(&edmaTransferConfig, (void *)&ADC1->R[1U], sizeof(uint16_t),
						 (void *)g_adcValues[ADC1_CHANNEL11_EDMA3], sizeof(uint16_t), sizeof(uint16_t),
						 sizeof(g_adcValues[ADC1_CHANNEL11_EDMA3]), kEDMA_PeripheralToMemory);
	EDMA_SubmitTransfer(&g_edmaHandle[ADC1_CHANNEL11_EDMA3], &edmaTransferConfig);

	DMA0->TCD[ADC1_CHANNEL11_EDMA3].DLAST_SGA = -(2U*ADC_BUFFER_SIZE*sizeof(uint16_t));	// reset to start address
	DMA0->TCD[ADC1_CHANNEL11_EDMA3].CSR &= ~DMA_CSR_DREQ_MASK;							// don't disable DMA REQ line

	/* Configure two Interrupts per buffer filling */
	EDMA_EnableChannelInterrupts(DMA0, ADC0_CHANNEL10_EDMA0, kEDMA_HalfInterruptEnable);
	EDMA_EnableChannelInterrupts(DMA0, ADC0_CHANNEL11_EDMA1, kEDMA_HalfInterruptEnable);
	EDMA_EnableChannelInterrupts(DMA0, ADC1_CHANNEL10_EDMA2, kEDMA_HalfInterruptEnable);
	EDMA_EnableChannelInterrupts(DMA0, ADC1_CHANNEL11_EDMA3, kEDMA_HalfInterruptEnable);
}

void ADC_Enable(void)
{
	vTaskResume(g_adcTaskHandle);
	PRINTF("ADC Task resumed\r\n");

	/* Start EDMA transfers */
	EDMA_StartTransfer(&g_edmaHandle[ADC0_CHANNEL10_EDMA0]);
	EDMA_StartTransfer(&g_edmaHandle[ADC0_CHANNEL11_EDMA1]);
	EDMA_StartTransfer(&g_edmaHandle[ADC1_CHANNEL10_EDMA2]);
	EDMA_StartTransfer(&g_edmaHandle[ADC1_CHANNEL11_EDMA3]);

	/* Start TPM counters */
	TPM_StartTimer(TPM1, kTPM_SystemClock);
	TPM_StartTimer(TPM2, kTPM_SystemClock);
}

void ADC_Disable(void)
{
	/* Stop TPM counters */
	TPM_StopTimer(TPM1);
	TPM_StopTimer(TPM2);

	/* Stop EDMA transfers */
	EDMA_StopTransfer(&g_edmaHandle[ADC0_CHANNEL10_EDMA0]);
	EDMA_StopTransfer(&g_edmaHandle[ADC0_CHANNEL11_EDMA1]);
	EDMA_StopTransfer(&g_edmaHandle[ADC1_CHANNEL10_EDMA2]);
	EDMA_StopTransfer(&g_edmaHandle[ADC1_CHANNEL11_EDMA3]);

	PRINTF("ADC Task suspended\r\n");
	vTaskSuspend(g_adcTaskHandle);
}

TaskHandle_t ADC_TaskInit(void)
{
	uint32_t tmp32;

	TaskHandle_t xCreatedTask, xReturn;
	portBASE_TYPE xResult;

	/* configure ADC0/ADC1 alternate trigger via TPM */
	tmp32 = SIM->SOPT7 & ~(SIM_SOPT7_ADC0TRGSEL_MASK | SIM_SOPT7_ADC1TRGSEL_MASK);
	tmp32 |= SIM_SOPT7_ADC1ALTTRGEN_MASK | SIM_SOPT7_ADC1TRGSEL(15U) | SIM_SOPT7_ADC0ALTTRGEN_MASK | SIM_SOPT7_ADC0TRGSEL(15U);
	SIM->SOPT7 = tmp32;

	TPM_Configuration();	/* Initialize TPM. */
	ADC16_Configuration();  /* Initialize ADC16. */
	DMAMUX_Configuration(); /* Initialize DMAMUX. */
	EDMA_Configuration();   /* Initialize EDMA. */

	g_adcQueue = xQueueCreate(10U, 1U);
	if(g_adcQueue == NULL)
	{
		throwError(ERROR_QUEUE_CREATION_FAILURE);
		PRINTF("%s ADC!\r\n", getErrorMessage(ERROR_QUEUE_CREATION_FAILURE));
		return NULL;
	}

	xResult = xTaskCreate(ADC_Task, "adc_task", TASK_STACKSIZE_ADC, NULL, TASK_PRIO_ADC, &xCreatedTask);
	if(xResult == pdPASS)
	{
		g_adcTaskHandle = xCreatedTask;
		xReturn = xCreatedTask;
	}
	else
	{
		throwError(ERROR_TASK_CREATION_FAILURE);
		PRINTF("%s ADC!\r\n", getErrorMessage(ERROR_TASK_CREATION_FAILURE));
		xReturn = NULL;
	}
	return xReturn;
}