LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY controller_tb IS
END ENTITY controller_tb;

ARCHITECTURE structural OF controllertb IS
	COMPONENT timebase IS
		PORT (
			clk : IN std_logic;
			reset : IN std_logic;

			count_out : OUT std_logic_vector (19 DOWNTO 0)
		);
	END COMPONENT timebase;

	COMPONENT controller IS
		PORT (
			clk : IN std_logic;
			reset : IN std_logic;

			count_in : IN std_logic_vector (19 DOWNTO 0);

			sensor_l : IN std_logic;
			sensor_m : IN std_logic;
			sensor_r : IN std_logic;

			motor_l_direction : OUT std_logic; -- '0' == ccw; '1' == cw
			motor_r_direction : OUT std_logic; -- '0' == ccw; '1' == cw

			count_reset : OUT std_logic;
			motor_l_reset : OUT std_logic;
			motor_r_reset : OUT std_logic
		);
	END COMPONENT controller;

	SIGNAL clk, reset : std_logic;
	SIGNAL sensor_l, sensor_m, sensor_r : std_logic;
	SIGNAL sensors : std_logic_vector(2 DOWNTO 0);
	SIGNAL motor_l_direction, motor_r_direction, count_reset, motor_l_reset, motor_r_reset : std_logic;

BEGIN
	lbl0 : timebase PORT MAP(
		clk => clk,
		reset => reset,
		count_out => count
	);

	lbl1 : controller PORT MAP(
		clk => clk,
		reset => reset,
		sensor_l_in => sensor_l,
		sensor_m_in => sensor_m,
		sensor_r_in => sensor_r,
		motor_l_direction => motor_l_direction,
		motor_r_direction => motor_r_direction,
		count_reset => count_reset,
		motor_l_reset => motor_l_reset,
		motor_r_reset => motor_r_reset,
		count_in => count
	);

	-- 20 ns = 50 MHz
	clk <= '0' AFTER 0 ns,
		'1' AFTER 10 ns WHEN clk /= '1' ELSE
		'0' AFTER 10 ns;

	reset <= '1' AFTER 0 ns,
		'0' AFTER 40 ms;

	sensors <= "000" AFTER 0 ns, -- bbb
		"001" AFTER 80 ms, -- bbw
		"010" AFTER 120 ms, -- bwb
		"011" AFTER 160 ms, -- bww
		"100" AFTER 200 ms, -- wbb
		"101" AFTER 240 ms, -- wbw
		"110" AFTER 280 ms, -- wwb
		"111" AFTER 320 ms; -- www

	sensor_l <= sensors(2);
	sensor_m <= sensors(1);
	sensor_r <= sensors(0);

END ARCHITECTURE structural;