APB_UVM_SLV_IF

interface apb_slv_intf #(
    parameter DATA_WIDTH    = 32,
    parameter ADDR_WIDTH    = 32
)(  input PCLK);

    logic PSEL;
    logic PWRITE;
    logic [(DATA_WIDTH-1):0] PWDATA;
    logic [(ADDR_WIDTH-1):0] PADDR;
    logic PREADY;
    logic PSLVERR;
    logic [(DATA_WIDTH-1):0] PRDATA;

    clocking slv_drv_cb @ (posedge PCLK);
        default input #1 output #1;

        output PREADY;
        output PSLVERR;
        output PRDATA;
    endclocking: slv_drv_cb

    clocking slv_mon_cb @ (posedge PCLK);
        default input #1 output #1;

        input PWRITE;
        input PWDATA;
        input PADDR;
        input PSEL;
        input PREADY;
        input PSLVERR;
        input PRDATA;
    endclocking: slv_mon_cb

    modport DST_DRV_MP (clocking slv_drv_cb);
    modport DST_MON_MP (clocking slv_mon_cb);

endinterface: apb_slv_intf