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  1. /* Copyright (c) 2009, Code Aurora Forum. All rights reserved.
  2. *
  3. * Redistribution and use in source and binary forms, with or without
  4. * modification, are permitted provided that the following conditions are met:
  5. * * Redistributions of source code must retain the above copyright
  6. * notice, this list of conditions and the following disclaimer.
  7. * * Redistributions in binary form must reproduce the above copyright
  8. * notice, this list of conditions and the following disclaimer in the
  9. * documentation and/or other materials provided with the distribution.
  10. * * Neither the name of Code Aurora Forum nor
  11. * the names of its contributors may be used to endorse or promote
  12. * products derived from this software without specific prior written
  13. * permission.
  14. *
  15. * Alternatively, provided that this notice is retained in full, this software
  16. * may be relicensed by the recipient under the terms of the GNU General Public
  17. * License version 2 ("GPL") and only version 2, in which case the provisions of
  18. * the GPL apply INSTEAD OF those given above. If the recipient relicenses the
  19. * software under the GPL, then the identification text in the MODULE_LICENSE
  20. * macro must be changed to reflect "GPLv2" instead of "Dual BSD/GPL". Once a
  21. * recipient changes the license terms to the GPL, subsequent recipients shall
  22. * not relicense under alternate licensing terms, including the BSD or dual
  23. * BSD/GPL terms. In addition, the following license statement immediately
  24. * below and between the words START and END shall also then apply when this
  25. * software is relicensed under the GPL:
  26. *
  27. * START
  28. *
  29. * This program is free software; you can redistribute it and/or modify it under
  30. * the terms of the GNU General Public License version 2 and only version 2 as
  31. * published by the Free Software Foundation.
  32. *
  33. * This program is distributed in the hope that it will be useful, but WITHOUT
  34. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
  35. * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
  36. * details.
  37. *
  38. * You should have received a copy of the GNU General Public License along with
  39. * this program; if not, write to the Free Software Foundation, Inc.,
  40. * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
  41. *
  42. * END
  43. *
  44. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  45. * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  46. * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  47. * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  48. * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  49. * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  50. * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  51. * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  52. * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  53. * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  54. * POSSIBILITY OF SUCH DAMAGE.
  55. *
  56. */
  57.  
  58. #include <linux/kernel.h>
  59. #include <linux/init.h>
  60. #include <linux/err.h>
  61. #include <linux/ctype.h>
  62. #include <linux/bitops.h>
  63. #include <linux/io.h>
  64. #include <linux/spinlock.h>
  65.  
  66. #include <mach/msm_iomap.h>
  67. #include <mach/clk.h>
  68. #include <mach/internal_power_rail.h>
  69.  
  70. #include "clock.h"
  71. #include "clock-7x30.h"
  72. #include "proc_comm.h"
  73.  
  74. enum {
  75. NOMINAL,
  76. HIGH,
  77. MSMC1_END
  78. };
  79.  
  80. struct clk_freq_tbl {
  81. uint32_t freq_hz;
  82. uint32_t src;
  83. uint32_t md_val;
  84. uint32_t ns_val;
  85. uint32_t mode;
  86. unsigned msmc1;
  87. };
  88.  
  89. struct clk_local {
  90. uint32_t count;
  91. uint32_t type;
  92. uint32_t md_reg;
  93. uint32_t ns_reg;
  94. uint32_t freq_mask;
  95. uint32_t br_en_mask;
  96. uint32_t root_en_mask;
  97. int parent;
  98. uint32_t *children;
  99. struct clk_freq_tbl *freq_tbl;
  100. struct clk_freq_tbl *current_freq;
  101. };
  102.  
  103.  
  104. enum {
  105. SRC_PLL0 = 4, /* Modem PLL */
  106. SRC_PLL1 = 1, /* Global PLL */
  107. SRC_PLL3 = 3, /* Multimedia/Peripheral PLL or Backup PLL1 */
  108. SRC_PLL4 = 2, /* Display PLL */
  109. SRC_LPXO = 6, /* Low power XO. */
  110. SRC_MAX /* Used for sources that can't be turned on/off. */
  111. };
  112.  
  113. static uint32_t src_pll_tbl[] = {
  114. [SRC_PLL0] = PLL_0,
  115. [SRC_PLL1] = PLL_1,
  116. [SRC_PLL3] = PLL_3,
  117. [SRC_PLL4] = PLL_4,
  118. };
  119.  
  120. #define B(x) BIT(x)
  121. #define BM(msb, lsb) (((((uint32_t)-1) << (31-msb)) >> (31-msb+lsb)) << lsb)
  122. #define BVAL(msb, lsb, val) (((val) << lsb) & BM(msb, lsb))
  123.  
  124. #define MD8(m, n) (BVAL(15, 8, m) | BVAL(7, 0, ~(n)))
  125. #define N8(msb, lsb, m, n) (BVAL(msb, lsb, ~(n-m)))
  126. #define MD16(m, n) (BVAL(31, 16, m) | BVAL(15, 0, ~(n)))
  127. #define N16(m, n) (BVAL(31, 16, ~(n-m)))
  128. #define SPDIV(s, d) (BVAL(4, 3, d-1) | BVAL(2, 0, s))
  129. #define SDIV(s, d) (BVAL(6, 3, d-1) | BVAL(2, 0, s))
  130. #define F_MASK_BASIC (BM(6, 3)|BM(2, 0))
  131. #define F_MASK_MND16 (BM(31, 16)|BM(4, 3)|BM(2, 0))
  132. #define F_MASK_MND8(m, l) (BM(m, l)|BM(4, 3)|BM(2, 0))
  133.  
  134. #define F_RAW(f, s, m_v, n_v, mde, v) { \
  135. .freq_hz = f, \
  136. .src = s, \
  137. .md_val = m_v, \
  138. .ns_val = n_v, \
  139. .mode = mde, \
  140. .msmc1 = v \
  141. }
  142.  
  143. #define FREQ_END 0
  144. #define F_BASIC(f, s, div, v) F_RAW(f, s, 0, SDIV(s, div), 0, v)
  145. #define F_MND16(f, s, div, m, n, v) \
  146. F_RAW(f, s, MD16(m, n), N16(m, n)|SPDIV(s, div), !!(n), v)
  147. #define F_MND8(f, nmsb, nlsb, s, div, m, n, v) \
  148. F_RAW(f, s, MD8(m, n), N8(nmsb, nlsb, m, n)|SPDIV(s, div), !!(n), v)
  149. #define F_END F_RAW(FREQ_END, SRC_MAX, 0, 0, 0, MSMC1_END)
  150.  
  151. static struct clk_freq_tbl clk_tbl_csi[] = {
  152. F_MND8(153600000, 24, 17, SRC_PLL1, 2, 2, 5, NOMINAL),
  153. F_MND8(192000000, 24, 17, SRC_PLL1, 4, 0, 0, NOMINAL),
  154. F_MND8(384000000, 24, 17, SRC_PLL1, 2, 0, 0, NOMINAL),
  155. F_END,
  156. };
  157.  
  158. static struct clk_freq_tbl clk_tbl_tcxo[] = {
  159. F_RAW(19200000, SRC_MAX, 0, 0, 0, NOMINAL),
  160. F_END,
  161. };
  162.  
  163. static struct clk_freq_tbl clk_tbl_uartdm[] = {
  164. F_MND16( 3686400, SRC_PLL3, 3, 3, 200, NOMINAL),
  165. F_MND16( 7372800, SRC_PLL3, 3, 3, 100, NOMINAL),
  166. F_MND16(14745600, SRC_PLL3, 3, 3, 50, NOMINAL),
  167. F_MND16(46400000, SRC_PLL3, 3, 145, 768, NOMINAL),
  168. F_MND16(51200000, SRC_PLL3, 3, 5, 24, NOMINAL),
  169. F_MND16(58982400, SRC_PLL3, 3, 6, 25, NOMINAL),
  170. F_MND16(64000000, SRC_PLL1, 4, 1, 3, NOMINAL),
  171. F_END,
  172. };
  173.  
  174. static struct clk_freq_tbl clk_tbl_mdh[] = {
  175. F_BASIC( 73728000, SRC_PLL3, 10, NOMINAL),
  176. F_BASIC( 92160000, SRC_PLL3, 8, NOMINAL),
  177. F_BASIC(122880000, SRC_PLL3, 6, NOMINAL),
  178. F_BASIC(184320000, SRC_PLL3, 4, NOMINAL),
  179. F_BASIC(245760000, SRC_PLL3, 3, NOMINAL),
  180. F_BASIC(368640000, SRC_PLL3, 2, NOMINAL),
  181. F_BASIC(384000000, SRC_PLL1, 2, NOMINAL),
  182. F_BASIC(445500000, SRC_PLL4, 2, NOMINAL),
  183. F_END,
  184. };
  185.  
  186. static struct clk_freq_tbl clk_tbl_grp[] = {
  187. F_BASIC( 24576000, SRC_LPXO, 1, NOMINAL),
  188. F_BASIC( 46080000, SRC_PLL3, 16, NOMINAL),
  189. F_BASIC( 49152000, SRC_PLL3, 15, NOMINAL),
  190. F_BASIC( 52662875, SRC_PLL3, 14, NOMINAL),
  191. F_BASIC( 56713846, SRC_PLL3, 13, NOMINAL),
  192. F_BASIC( 61440000, SRC_PLL3, 12, NOMINAL),
  193. F_BASIC( 67025454, SRC_PLL3, 11, NOMINAL),
  194. F_BASIC( 73728000, SRC_PLL3, 10, NOMINAL),
  195. F_BASIC( 81920000, SRC_PLL3, 9, NOMINAL),
  196. F_BASIC( 92160000, SRC_PLL3, 8, NOMINAL),
  197. F_BASIC(105325714, SRC_PLL3, 7, NOMINAL),
  198. F_BASIC(122880000, SRC_PLL3, 6, NOMINAL),
  199. F_BASIC(147456000, SRC_PLL3, 5, NOMINAL),
  200. F_BASIC(184320000, SRC_PLL3, 4, NOMINAL),
  201. F_BASIC(192000000, SRC_PLL1, 4, NOMINAL),
  202. F_BASIC(245760000, SRC_PLL3, 3, HIGH),
  203. /* Sync to AXI. Hence this "rate" is not fixed. */
  204. F_RAW(1, SRC_MAX, 0, B(14), 0, NOMINAL),
  205. F_END,
  206. };
  207.  
  208. static struct clk_freq_tbl clk_tbl_sdc1_3[] = {
  209. F_MND8( 144000, 19, 12, SRC_LPXO, 1, 1, 171, NOMINAL),
  210. F_MND8( 400000, 19, 12, SRC_LPXO, 1, 2, 123, NOMINAL),
  211. F_MND8(16027000, 19, 12, SRC_PLL3, 3, 14, 215, NOMINAL),
  212. F_MND8(17000000, 19, 12, SRC_PLL3, 4, 19, 206, NOMINAL),
  213. F_MND8(20480000, 19, 12, SRC_PLL3, 4, 23, 212, NOMINAL),
  214. F_MND8(24576000, 19, 12, SRC_LPXO, 1, 0, 0, NOMINAL),
  215. F_MND8(49152000, 19, 12, SRC_PLL3, 3, 1, 5, NOMINAL),
  216. F_END,
  217. };
  218.  
  219. static struct clk_freq_tbl clk_tbl_sdc2_4[] = {
  220. F_MND8( 144000, 20, 13, SRC_LPXO, 1, 1, 171, NOMINAL),
  221. F_MND8( 400000, 20, 13, SRC_LPXO, 1, 2, 123, NOMINAL),
  222. F_MND8(16027000, 20, 13, SRC_PLL3, 3, 14, 215, NOMINAL),
  223. F_MND8(17000000, 20, 13, SRC_PLL3, 4, 19, 206, NOMINAL),
  224. F_MND8(20480000, 20, 13, SRC_PLL3, 4, 23, 212, NOMINAL),
  225. F_MND8(24576000, 20, 13, SRC_LPXO, 1, 0, 0, NOMINAL),
  226. F_MND8(49152000, 20, 13, SRC_PLL3, 3, 1, 5, NOMINAL),
  227. F_END,
  228. };
  229.  
  230. static struct clk_freq_tbl clk_tbl_mdp_core[] = {
  231. F_BASIC( 46080000, SRC_PLL3, 16, NOMINAL),
  232. F_BASIC( 49152000, SRC_PLL3, 15, NOMINAL),
  233. F_BASIC( 52663000, SRC_PLL3, 14, NOMINAL),
  234. F_BASIC( 92160000, SRC_PLL3, 8, NOMINAL),
  235. F_BASIC(122880000, SRC_PLL3, 6, NOMINAL),
  236. F_BASIC(147456000, SRC_PLL3, 5, NOMINAL),
  237. F_BASIC(153600000, SRC_PLL1, 5, NOMINAL),
  238. F_BASIC(192000000, SRC_PLL1, 4, HIGH),
  239. F_END,
  240. };
  241.  
  242. static struct clk_freq_tbl clk_tbl_mdp_lcdc[] = {
  243. F_MND16(24576000, SRC_LPXO, 1, 0, 0, NOMINAL),
  244. F_MND16(30720000, SRC_PLL3, 4, 1, 6, NOMINAL),
  245. F_MND16(40960000, SRC_PLL3, 2, 1, 9, NOMINAL),
  246. F_END,
  247. };
  248.  
  249. static struct clk_freq_tbl clk_tbl_mdp_vsync[] = {
  250. F_RAW(24576000, SRC_LPXO, 0, 0, 0, NOMINAL),
  251. F_END,
  252. };
  253.  
  254. static struct clk_freq_tbl clk_tbl_mi2s_codec[] = {
  255. F_MND16( 2048000, SRC_LPXO, 4, 1, 3, NOMINAL),
  256. F_MND16(12288000, SRC_LPXO, 2, 0, 0, NOMINAL),
  257. F_END,
  258. };
  259.  
  260. static struct clk_freq_tbl clk_tbl_mi2s[] = {
  261. F_MND16(12288000, SRC_LPXO, 2, 0, 0, NOMINAL),
  262. F_END,
  263. };
  264.  
  265. static struct clk_freq_tbl clk_tbl_midi[] = {
  266. F_MND8(98304000, 19, 12, SRC_PLL3, 3, 2, 5, NOMINAL),
  267. F_END,
  268. };
  269. static struct clk_freq_tbl clk_tbl_sdac[] = {
  270. F_MND16( 256000, SRC_LPXO, 4, 1, 24, NOMINAL),
  271. F_MND16( 352800, SRC_LPXO, 1, 147, 10240, NOMINAL),
  272. F_MND16( 384000, SRC_LPXO, 4, 1, 16, NOMINAL),
  273. F_MND16( 512000, SRC_LPXO, 4, 1, 12, NOMINAL),
  274. F_MND16( 705600, SRC_LPXO, 1, 147, 5120, NOMINAL),
  275. F_MND16( 768000, SRC_LPXO, 4, 1, 8, NOMINAL),
  276. F_MND16(1024000, SRC_LPXO, 4, 1, 6, NOMINAL),
  277. F_MND16(1411200, SRC_LPXO, 1, 147, 2560, NOMINAL),
  278. F_MND16(1536000, SRC_LPXO, 4, 1, 4, NOMINAL),
  279. F_END,
  280. };
  281.  
  282. static struct clk_freq_tbl clk_tbl_tv[] = {
  283. F_MND8(27000000, 23, 16, SRC_PLL4, 2, 2, 33, NOMINAL),
  284. F_MND8(74250000, 23, 16, SRC_PLL4, 2, 1, 6, NOMINAL),
  285. F_END,
  286. };
  287.  
  288. static struct clk_freq_tbl clk_tbl_usb[] = {
  289. F_MND8(60000000, 23, 16, SRC_PLL1, 2, 5, 32, NOMINAL),
  290. F_END,
  291. };
  292.  
  293. static struct clk_freq_tbl clk_tbl_vfe_jpeg[] = {
  294. F_MND16( 36864000, SRC_PLL3, 4, 1, 5, NOMINAL),
  295. F_MND16( 46080000, SRC_PLL3, 4, 1, 4, NOMINAL),
  296. F_MND16( 61440000, SRC_PLL3, 4, 1, 3, NOMINAL),
  297. F_MND16( 73728000, SRC_PLL3, 2, 1, 5, NOMINAL),
  298. F_MND16( 81920000, SRC_PLL3, 3, 1, 3, NOMINAL),
  299. F_MND16( 92160000, SRC_PLL3, 4, 1, 2, NOMINAL),
  300. F_MND16( 98304000, SRC_PLL3, 3, 2, 5, NOMINAL),
  301. F_MND16(105326000, SRC_PLL3, 2, 2, 7, NOMINAL),
  302. F_MND16(122880000, SRC_PLL3, 2, 1, 3, NOMINAL),
  303. F_MND16(147456000, SRC_PLL3, 2, 2, 5, NOMINAL),
  304. F_MND16(153600000, SRC_PLL1, 2, 2, 5, NOMINAL),
  305. F_END,
  306. };
  307.  
  308. static struct clk_freq_tbl clk_tbl_cam[] = {
  309. F_MND16( 6000000, SRC_PLL1, 4, 1, 32, NOMINAL),
  310. F_MND16( 8000000, SRC_PLL1, 4, 1, 24, NOMINAL),
  311. F_MND16(12000000, SRC_PLL1, 4, 1, 16, NOMINAL),
  312. F_MND16(16000000, SRC_PLL1, 4, 1, 12, NOMINAL),
  313. F_MND16(19200000, SRC_PLL1, 4, 1, 10, NOMINAL),
  314. F_MND16(24000000, SRC_PLL1, 4, 1, 8, NOMINAL),
  315. F_MND16(32000000, SRC_PLL1, 4, 1, 6, NOMINAL),
  316. F_MND16(48000000, SRC_PLL1, 4, 1, 4, NOMINAL),
  317. F_MND16(64000000, SRC_PLL1, 4, 1, 3, NOMINAL),
  318. F_END,
  319. };
  320.  
  321. static struct clk_freq_tbl clk_tbl_vpe[] = {
  322. F_MND8( 24576000, 22, 15, SRC_LPXO, 1, 0, 0, NOMINAL),
  323. F_MND8( 30720000, 22, 15, SRC_PLL3, 4, 1, 6, NOMINAL),
  324. F_MND8( 61440000, 22, 15, SRC_PLL3, 4, 1, 3, NOMINAL),
  325. F_MND8( 81920000, 22, 15, SRC_PLL3, 3, 1, 3, NOMINAL),
  326. F_MND8(122880000, 22, 15, SRC_PLL3, 3, 1, 2, NOMINAL),
  327. F_MND8(147456000, 22, 15, SRC_PLL3, 1, 1, 5, NOMINAL),
  328. F_MND8(153600000, 22, 15, SRC_PLL1, 1, 1, 5, NOMINAL),
  329. F_END,
  330. };
  331.  
  332. static struct clk_freq_tbl clk_tbl_mfc[] = {
  333. F_MND8( 24576000, 24, 17, SRC_LPXO, 1, 0, 0, NOMINAL),
  334. F_MND8( 30720000, 24, 17, SRC_PLL3, 4, 1, 6, NOMINAL),
  335. F_MND8( 61440000, 24, 17, SRC_PLL3, 4, 1, 3, NOMINAL),
  336. F_MND8( 81920000, 24, 17, SRC_PLL3, 3, 1, 3, NOMINAL),
  337. F_MND8(122880000, 24, 17, SRC_PLL3, 3, 1, 2, NOMINAL),
  338. F_MND8(147456000, 24, 17, SRC_PLL3, 1, 1, 5, NOMINAL),
  339. F_MND8(153600000, 24, 17, SRC_PLL1, 1, 1, 5, NOMINAL),
  340. F_MND8(170667000, 24, 17, SRC_PLL1, 1, 2, 9, NOMINAL),
  341. F_END,
  342. };
  343.  
  344. static struct clk_freq_tbl clk_tbl_spi[] = {
  345. F_MND8( 9963243, 19, 12, SRC_PLL3, 4, 7, 129, NOMINAL),
  346. F_MND8(26331429, 19, 12, SRC_PLL3, 4, 34, 241, NOMINAL),
  347. F_END,
  348. };
  349.  
  350. static struct clk_freq_tbl clk_tbl_lpa_codec[] = {
  351. F_RAW(1, SRC_MAX, 0, 0, 0, MSMC1_END), /* src = MI2S_CODEC_RX */
  352. F_RAW(2, SRC_MAX, 0, 1, 0, MSMC1_END), /* src = ECODEC_CIF */
  353. F_RAW(3, SRC_MAX, 0, 2, 0, MSMC1_END), /* src = MI2S */
  354. F_RAW(4, SRC_MAX, 0, 3, 0, MSMC1_END), /* src = SDAC */
  355. F_END,
  356. };
  357.  
  358. static struct clk_freq_tbl dummy_freq = F_END;
  359.  
  360. #define MND 1 /* Integer predivider and fractional MN:D divider. */
  361. #define BASIC 2 /* Integer divider. */
  362. #define NORATE 3 /* Just on/off. */
  363.  
  364. #define C(x) L_7X30_##x##_CLK
  365.  
  366. #define CLK_LOCAL(id, t, md, ns, f_msk, br, root, tbl, par, chld_lst) \
  367. [C(id)] = { \
  368. .type = t, \
  369. .md_reg = md, \
  370. .ns_reg = ns, \
  371. .freq_mask = f_msk, \
  372. .br_en_mask = br, \
  373. .root_en_mask = root, \
  374. .parent = C(par), \
  375. .children = chld_lst, \
  376. .freq_tbl = tbl, \
  377. .current_freq = &dummy_freq, \
  378. }
  379.  
  380. #define CLK_BASIC(id, ns, br, root, tbl, par) \
  381. CLK_LOCAL(id, BASIC, 0, ns, F_MASK_BASIC, br, root, tbl, \
  382. par, NULL)
  383. #define CLK_MND8_P(id, ns, m, l, br, root, tbl, par, chld_lst) \
  384. CLK_LOCAL(id, MND, (ns-4), ns, F_MASK_MND8(m, l), br, root, \
  385. tbl, par, chld_lst)
  386. #define CLK_MND8(id, ns, m, l, br, root, tbl, chld_lst) \
  387. CLK_MND8_P(id, ns, m, l, br, root, tbl, NONE, chld_lst)
  388. #define CLK_MND16(id, ns, br, root, tbl, par, chld_lst) \
  389. CLK_LOCAL(id, MND, (ns-4), ns, F_MASK_MND16, br, root, tbl, \
  390. par, chld_lst)
  391. #define CLK_1RATE(id, ns, br, root, tbl) \
  392. CLK_LOCAL(id, BASIC, 0, ns, 0, br, root, tbl, NONE, NULL)
  393. #define CLK_SLAVE(id, ns, br, par) \
  394. CLK_LOCAL(id, NORATE, 0, ns, 0, br, 0, NULL, par, NULL)
  395. #define CLK_NORATE(id, ns, br, root) \
  396. CLK_LOCAL(id, NORATE, 0, ns, 0, br, root, NULL, NONE, NULL)
  397. #define CLK_GLBL(id, glbl, root) \
  398. CLK_LOCAL(id, NORATE, 0, glbl, 0, 0, root, NULL, \
  399. GLBL_ROOT, NULL)
  400. #define CLK_BRIDGE(id, glbl, root, par) \
  401. CLK_LOCAL(id, NORATE, 0, glbl, 0, 0, root, NULL, par, NULL)
  402.  
  403. #define REG_BASE(off) (MSM_CLK_CTL_BASE + off)
  404. #define REG(off) (MSM_CLK_CTL_SH2_BASE + off)
  405. #define MNCNTR_EN_MASK B(8)
  406. #define MNCNTR_RST_MASK B(7)
  407. #define MNCNTR_MODE_MASK BM(6, 5)
  408. #define MNCNTR_MODE BVAL(6, 5, 0x2) /* Dual-edge mode. */
  409.  
  410. /* Register offsets used more than once. */
  411. #define CSI_NS 0x0174
  412. #define EMDH_NS 0x0050
  413. #define PMDH_NS 0x008C
  414. #define UART_NS 0x00E0
  415. #define UART2_NS 0x0464
  416. #define USBH_MD 0x02BC
  417. #define USBH_NS 0x02C0
  418. #define USBH2_NS 0x046C
  419. #define USBH3_NS 0x0470
  420. #define CAM_VFE_NS 0x0044
  421. #define GLBL_CLK_ENA_SC 0x03BC
  422. #define GLBL_CLK_ENA_2_SC 0x03C0
  423. #define GRP_NS 0x0084
  424. #define SDAC_NS 0x009C
  425. #define TV_NS 0x00CC
  426. #define HDMI_NS 0x0484
  427. #define MI2S_RX_NS 0x0070
  428. #define MI2S_TX_NS 0x0078
  429. #define MI2S_NS 0x02E0
  430. #define MFC_NS 0x0154
  431. #define LPA_NS 0x02E8
  432. #define MDC_NS 0x007C
  433. #define MDP_LCDC_NS 0x0390
  434. #define MDP_VSYNC_REG 0x0460
  435.  
  436. #if CONFIG_MSM_AMSS_VERSION >= 1200
  437. #define PLL_ENA_REG 0x0264
  438. #else
  439. #define PLL_ENA_REG 0x0260
  440. #endif
  441.  
  442. #define LPA_CORE_CLK_MA0 0x04F4
  443. #define LPA_CORE_CLK_MA2 0x04FC
  444. #define SH2_OWN_GLBL_REG 0x0404
  445. #define SH2_OWN_APPS1_REG 0x040C
  446. #define SH2_OWN_APPS2_REG 0x0414
  447. #define SH2_OWN_ROW1_REG 0x041C
  448. #define SH2_OWN_ROW2_REG 0x0424
  449. #define SH2_OWN_APPS3_REG 0x0444
  450.  
  451. static uint32_t *pll_status_addr[NUM_PLL] = {
  452. [PLL_0] = REG_BASE(0x318),
  453. [PLL_1] = REG_BASE(0x334),
  454. [PLL_2] = REG_BASE(0x350),
  455. [PLL_3] = REG_BASE(0x36C),
  456. [PLL_4] = REG_BASE(0x254),
  457. [PLL_5] = REG_BASE(0x258),
  458. [PLL_6] = REG_BASE(0x4EC),
  459. };
  460.  
  461. static uint32_t pll_count[NUM_PLL];
  462.  
  463. static uint32_t chld_grp_3d_src[] = {C(IMEM), C(GRP_3D), C(NONE)};
  464. static uint32_t chld_mdp_lcdc_p[] = {C(MDP_LCDC_PAD_PCLK), C(NONE)};
  465. static uint32_t chld_mfc[] = {C(MFC_DIV2), C(NONE)};
  466. static uint32_t chld_mi2s_codec_rx[] = {C(MI2S_CODEC_RX_S), C(NONE)};
  467. static uint32_t chld_mi2s_codec_tx[] = {C(MI2S_CODEC_TX_S), C(NONE)};
  468. static uint32_t chld_mi2s[] = {C(MI2S_S), C(NONE)};
  469. static uint32_t chld_sdac[] = {C(SDAC_M), C(NONE)};
  470. static uint32_t chld_tv[] = {C(TV_DAC), C(TV_ENC), C(TSIF_REF),
  471. C(HDMI), C(NONE)};
  472. static uint32_t chld_usb_src[] = {C(USB_HS), C(USB_HS_CORE),
  473. C(USB_HS2), C(USB_HS2_CORE),
  474. C(USB_HS3), C(USB_HS3_CORE),
  475. C(NONE)};
  476. uint32_t chld_vfe[] = {C(VFE_MDC), C(VFE_CAMIF), C(CSI0_VFE),
  477. C(NONE)};
  478.  
  479. static struct clk_local clk_local_tbl[] = {
  480. CLK_NORATE(MDC, MDC_NS, B(9), B(11)),
  481. CLK_NORATE(LPA_CORE, LPA_NS, B(5), 0),
  482.  
  483. CLK_1RATE(I2C, 0x0068, B(9), B(11), clk_tbl_tcxo),
  484. CLK_1RATE(I2C_2, 0x02D8, B(0), B(2), clk_tbl_tcxo),
  485. CLK_1RATE(QUP_I2C, 0x04F0, B(0), B(2), clk_tbl_tcxo),
  486. CLK_1RATE(UART1, UART_NS, B(5), B(4), clk_tbl_tcxo),
  487. CLK_1RATE(UART2, UART2_NS, B(5), B(4), clk_tbl_tcxo),
  488.  
  489. CLK_BASIC(EMDH, EMDH_NS, 0, B(11), clk_tbl_mdh, AXI_LI_ADSP_A),
  490. CLK_BASIC(PMDH, PMDH_NS, 0, B(11), clk_tbl_mdh, AXI_LI_ADSP_A),
  491. CLK_BASIC(MDP, 0x014C, B(9), B(11), clk_tbl_mdp_core, AXI_MDP),
  492.  
  493. CLK_MND8_P(VPE, 0x015C, 22, 15, B(9), B(11), clk_tbl_vpe,
  494. AXI_VPE, NULL),
  495. CLK_MND8_P(MFC, MFC_NS, 24, 17, B(9), B(11), clk_tbl_mfc,
  496. AXI_MFC, chld_mfc),
  497. CLK_SLAVE(MFC_DIV2, MFC_NS, B(15), MFC),
  498.  
  499. CLK_MND8(SDC1, 0x00A4, 19, 12, B(9), B(11), clk_tbl_sdc1_3, NULL),
  500. CLK_MND8(SDC2, 0x00AC, 20, 13, B(9), B(11), clk_tbl_sdc2_4, NULL),
  501. CLK_MND8(SDC3, 0x00B4, 19, 12, B(9), B(11), clk_tbl_sdc1_3, NULL),
  502. CLK_MND8(SDC4, 0x00BC, 20, 13, B(9), B(11), clk_tbl_sdc2_4, NULL),
  503. CLK_MND8(SPI, 0x02C8, 19, 12, B(9), B(11), clk_tbl_spi, NULL),
  504. CLK_MND8(MIDI, 0x02D0, 19, 12, B(9), B(11), clk_tbl_midi, NULL),
  505. CLK_MND8_P(USB_HS_SRC, USBH_NS, 23, 16, 0, B(11), clk_tbl_usb,
  506. AXI_LI_ADSP_A, chld_usb_src),
  507. CLK_SLAVE(USB_HS, USBH_NS, B(9), USB_HS_SRC),
  508. CLK_SLAVE(USB_HS_CORE, USBH_NS, B(13), USB_HS_SRC),
  509. CLK_SLAVE(USB_HS2, USBH2_NS, B(9), USB_HS_SRC),
  510. CLK_SLAVE(USB_HS2_CORE, USBH2_NS, B(4), USB_HS_SRC),
  511. CLK_SLAVE(USB_HS3, USBH3_NS, B(9), USB_HS_SRC),
  512. CLK_SLAVE(USB_HS3_CORE, USBH3_NS, B(4), USB_HS_SRC),
  513. CLK_MND8(TV, TV_NS, 23, 16, 0, B(11), clk_tbl_tv, chld_tv),
  514. CLK_SLAVE(HDMI, HDMI_NS, B(9), TV),
  515. CLK_SLAVE(TV_DAC, TV_NS, B(12), TV),
  516. CLK_SLAVE(TV_ENC, TV_NS, B(9), TV),
  517. /* Hacking root & branch into one param. */
  518. CLK_SLAVE(TSIF_REF, 0x00C4, B(9)|B(11), TV),
  519.  
  520. CLK_MND16(UART1DM, 0x00D4, B(9), B(11), clk_tbl_uartdm, NONE, NULL),
  521. CLK_MND16(UART2DM, 0x00DC, B(9), B(11), clk_tbl_uartdm, NONE, NULL),
  522. CLK_MND16(JPEG, 0x0164, B(9), B(11), clk_tbl_vfe_jpeg,
  523. AXI_LI_JPEG, NULL),
  524. CLK_MND16(CAM_M, 0x0374, 0, B(9), clk_tbl_cam, NONE, NULL),
  525. CLK_MND16(VFE, CAM_VFE_NS, B(9), B(13), clk_tbl_vfe_jpeg,
  526. AXI_LI_VFE, chld_vfe),
  527. CLK_SLAVE(VFE_MDC, CAM_VFE_NS, B(11), VFE),
  528. CLK_SLAVE(VFE_CAMIF, CAM_VFE_NS, B(15), VFE),
  529. CLK_SLAVE(CSI0_VFE, CSI_NS, B(15), VFE),
  530.  
  531. CLK_MND16(SDAC, SDAC_NS, B(9), B(11), clk_tbl_sdac,
  532. NONE, chld_sdac),
  533. CLK_SLAVE(SDAC_M, SDAC_NS, B(12), SDAC),
  534.  
  535. CLK_MND16(MDP_LCDC_PCLK, MDP_LCDC_NS, B(9), B(11), clk_tbl_mdp_lcdc,
  536. NONE, chld_mdp_lcdc_p),
  537. CLK_SLAVE(MDP_LCDC_PAD_PCLK, MDP_LCDC_NS, B(12), MDP_LCDC_PCLK),
  538. CLK_1RATE(MDP_VSYNC, MDP_VSYNC_REG, B(0), 0, clk_tbl_mdp_vsync),
  539.  
  540. CLK_MND16(MI2S_CODEC_RX_M, MI2S_RX_NS, B(12), B(11),
  541. clk_tbl_mi2s_codec, NONE, chld_mi2s_codec_rx),
  542. CLK_SLAVE(MI2S_CODEC_RX_S, MI2S_RX_NS, B(9), MI2S_CODEC_RX_M),
  543.  
  544. CLK_MND16(MI2S_CODEC_TX_M, MI2S_TX_NS, B(12), B(11),
  545. clk_tbl_mi2s_codec, NONE, chld_mi2s_codec_tx),
  546. CLK_SLAVE(MI2S_CODEC_TX_S, MI2S_TX_NS, B(9), MI2S_CODEC_TX_M),
  547.  
  548. CLK_MND16(MI2S_M, MI2S_NS, B(12), B(11),
  549. clk_tbl_mi2s, NONE, chld_mi2s),
  550. CLK_SLAVE(MI2S_S, MI2S_NS, B(9), MI2S_M),
  551.  
  552. CLK_LOCAL(GRP_2D, BASIC, 0, 0x0034, F_MASK_BASIC | (7 << 12),
  553. B(7), B(11), clk_tbl_grp, AXI_GRP_2D, NULL),
  554. CLK_LOCAL(GRP_3D_SRC, BASIC, 0, GRP_NS, F_MASK_BASIC | (7 << 12),
  555. 0, B(11), clk_tbl_grp, AXI_LI_GRP, chld_grp_3d_src),
  556. CLK_SLAVE(GRP_3D, GRP_NS, B(7), GRP_3D_SRC),
  557. CLK_SLAVE(IMEM, GRP_NS, B(9), GRP_3D_SRC),
  558. CLK_LOCAL(LPA_CODEC, BASIC, 0, LPA_NS, BM(1, 0), B(9), 0,
  559. clk_tbl_lpa_codec, NONE, NULL),
  560.  
  561. CLK_MND8(CSI0, CSI_NS, 24, 17, B(9), B(11), clk_tbl_csi, NULL),
  562.  
  563. /* For global clocks to be on we must have GLBL_ROOT_ENA set */
  564. CLK_NORATE(GLBL_ROOT, GLBL_CLK_ENA_SC, 0, B(29)),
  565.  
  566. /* Peripheral bus clocks. */
  567. CLK_GLBL(ADM, GLBL_CLK_ENA_SC, B(5)),
  568. CLK_GLBL(CAMIF_PAD_P, GLBL_CLK_ENA_SC, B(9)),
  569. CLK_GLBL(CSI0_P, GLBL_CLK_ENA_SC, B(30)),
  570. CLK_GLBL(EMDH_P, GLBL_CLK_ENA_2_SC, B(3)),
  571. CLK_GLBL(GRP_2D_P, GLBL_CLK_ENA_SC, B(24)),
  572. CLK_GLBL(GRP_3D_P, GLBL_CLK_ENA_2_SC, B(17)),
  573. CLK_GLBL(JPEG_P, GLBL_CLK_ENA_2_SC, B(24)),
  574. CLK_GLBL(LPA_P, GLBL_CLK_ENA_2_SC, B(7)),
  575. CLK_GLBL(MDP_P, GLBL_CLK_ENA_2_SC, B(6)),
  576. CLK_GLBL(MFC_P, GLBL_CLK_ENA_2_SC, B(26)),
  577. CLK_GLBL(PMDH_P, GLBL_CLK_ENA_2_SC, B(4)),
  578. CLK_GLBL(ROTATOR_IMEM, GLBL_CLK_ENA_2_SC, B(23)),
  579. CLK_GLBL(ROTATOR_P, GLBL_CLK_ENA_2_SC, B(25)),
  580. CLK_GLBL(SDC1_P, GLBL_CLK_ENA_SC, B(7)),
  581. CLK_GLBL(SDC2_P, GLBL_CLK_ENA_SC, B(8)),
  582. CLK_GLBL(SDC3_P, GLBL_CLK_ENA_SC, B(27)),
  583. CLK_GLBL(SDC4_P, GLBL_CLK_ENA_SC, B(28)),
  584. CLK_GLBL(SPI_P, GLBL_CLK_ENA_2_SC, B(10)),
  585. CLK_GLBL(TSIF_P, GLBL_CLK_ENA_SC, B(18)),
  586. CLK_GLBL(UART1DM_P, GLBL_CLK_ENA_SC, B(17)),
  587. CLK_GLBL(UART2DM_P, GLBL_CLK_ENA_SC, B(26)),
  588. CLK_GLBL(USB_HS2_P, GLBL_CLK_ENA_2_SC, B(8)),
  589. CLK_GLBL(USB_HS3_P, GLBL_CLK_ENA_2_SC, B(9)),
  590. CLK_GLBL(USB_HS_P, GLBL_CLK_ENA_SC, B(25)),
  591. CLK_GLBL(VFE_P, GLBL_CLK_ENA_2_SC, B(27)),
  592.  
  593. /* AXI bridge clocks. */
  594. CLK_BRIDGE(AXI_LI_APPS, GLBL_CLK_ENA_SC, B(2), GLBL_ROOT),
  595. CLK_BRIDGE(AXI_LI_ADSP_A, GLBL_CLK_ENA_2_SC, B(14), AXI_LI_APPS),
  596. CLK_BRIDGE(AXI_LI_JPEG, GLBL_CLK_ENA_2_SC, B(19), AXI_LI_APPS),
  597. CLK_BRIDGE(AXI_LI_VFE, GLBL_CLK_ENA_SC, B(23), AXI_LI_APPS),
  598. CLK_BRIDGE(AXI_MDP, GLBL_CLK_ENA_2_SC, B(29), AXI_LI_APPS),
  599.  
  600. CLK_BRIDGE(AXI_IMEM, GLBL_CLK_ENA_2_SC, B(18), GLBL_ROOT),
  601.  
  602. CLK_BRIDGE(AXI_LI_VG, GLBL_CLK_ENA_SC, B(3), GLBL_ROOT),
  603. CLK_BRIDGE(AXI_GRP_2D, GLBL_CLK_ENA_SC, B(21), AXI_LI_VG),
  604. CLK_BRIDGE(AXI_LI_GRP, GLBL_CLK_ENA_SC, B(22), AXI_LI_VG),
  605. CLK_BRIDGE(AXI_MFC, GLBL_CLK_ENA_2_SC, B(20), AXI_LI_VG),
  606. CLK_BRIDGE(AXI_ROTATOR, GLBL_CLK_ENA_2_SC, B(22), AXI_LI_VG),
  607. CLK_BRIDGE(AXI_VPE, GLBL_CLK_ENA_2_SC, B(21), AXI_LI_VG),
  608. };
  609.  
  610. static DEFINE_SPINLOCK(clock_reg_lock);
  611. static DEFINE_SPINLOCK(pll_vote_lock);
  612.  
  613. #define PLL_ACTIVE_MASK B(16)
  614. void pll_enable(uint32_t pll)
  615. {
  616. uint32_t reg_val;
  617. unsigned long flags;
  618.  
  619. BUG_ON(pll >= NUM_PLL);
  620.  
  621. spin_lock_irqsave(&pll_vote_lock, flags);
  622. if (!pll_count[pll]) {
  623. #if CONFIG_MSM_AMSS_VERSION >= 1200
  624. reg_val = readl(REG(PLL_ENA_REG));
  625. reg_val |= (1 << pll);
  626. writel(reg_val, REG(PLL_ENA_REG));
  627. #else
  628. reg_val = readl(REG_BASE(PLL_ENA_REG));
  629. reg_val |= (1 << pll);
  630. writel(reg_val, REG_BASE(PLL_ENA_REG));
  631. #endif
  632. }
  633. pll_count[pll]++;
  634. spin_unlock_irqrestore(&pll_vote_lock, flags);
  635.  
  636. /* Wait until PLL is enabled. */
  637. while ((readl(pll_status_addr[pll]) & PLL_ACTIVE_MASK) == 0)
  638. ;
  639. }
  640.  
  641. static void src_enable(uint32_t src)
  642. {
  643. /* SRC_MAX is used as a placeholder for some freqencies that don't
  644. * have any direct PLL dependency. */
  645. if (src == SRC_MAX || src == SRC_LPXO)
  646. return;
  647.  
  648. pll_enable(src_pll_tbl[src]);
  649. }
  650.  
  651. void pll_disable(uint32_t pll)
  652. {
  653. uint32_t reg_val;
  654. unsigned long flags;
  655.  
  656. BUG_ON(pll >= NUM_PLL);
  657.  
  658. spin_lock_irqsave(&pll_vote_lock, flags);
  659. if (pll_count[pll])
  660. pll_count[pll]--;
  661. else
  662. pr_warning("Reference count mismatch in PLL disable!\n");
  663.  
  664. if (pll_count[pll] == 0) {
  665. #if CONFIG_MSM_AMSS_VERSION >= 1200
  666. reg_val = readl(REG(PLL_ENA_REG));
  667. reg_val &= ~(1 << pll);
  668. writel(reg_val, REG(PLL_ENA_REG));
  669. #else
  670. reg_val = readl(REG_BASE(PLL_ENA_REG));
  671. reg_val &= ~(1 << pll);
  672. writel(reg_val, REG_BASE(PLL_ENA_REG));
  673. #endif
  674. }
  675. spin_unlock_irqrestore(&pll_vote_lock, flags);
  676. }
  677.  
  678. static void src_disable(uint32_t src)
  679. {
  680. /* SRC_MAX is used as a placeholder for some freqencies that don't
  681. * have any direct PLL dependency. */
  682. if (src == SRC_MAX || src == SRC_LPXO)
  683. return;
  684.  
  685. pll_disable(src_pll_tbl[src]);
  686.  
  687. }
  688.  
  689. static unsigned msmc1_votes[MSMC1_END];
  690. static unsigned msmc1_level;
  691.  
  692. static int update_msmc1(void)
  693. {
  694. int err, target, mvolts;
  695.  
  696. target = mvolts = msmc1_votes[HIGH] ? 1200 : 1100;
  697.  
  698. if (target == msmc1_level)
  699. return 0;
  700.  
  701. err = msm_proc_comm(PCOM_CLKCTL_RPC_MIN_MSMC1, &mvolts, NULL);
  702. if (err)
  703. goto out;
  704. if (mvolts) {
  705. err = -EINVAL;
  706. goto out;
  707. }
  708. msmc1_level = target;
  709. out:
  710. return err;
  711. }
  712.  
  713. static void unvote_msmc1(unsigned level)
  714. {
  715. if (level >= ARRAY_SIZE(msmc1_votes))
  716. return;
  717.  
  718. if (msmc1_votes[level]) {
  719. msmc1_votes[level]--;
  720. } else {
  721. pr_warning("%s: Reference counts are incorrect\n", __func__);
  722. return;
  723. }
  724.  
  725. update_msmc1();
  726. }
  727.  
  728. static int vote_msmc1(unsigned level)
  729. {
  730. int ret;
  731.  
  732. if (level >= ARRAY_SIZE(msmc1_votes))
  733. return 0;
  734.  
  735. msmc1_votes[level]++;
  736. ret = update_msmc1();
  737. if (ret)
  738. msmc1_votes[level]--;
  739.  
  740. return ret;
  741. }
  742.  
  743. /*
  744. * SoC specific register-based control of clocks.
  745. */
  746. static int _soc_clk_enable(unsigned id)
  747. {
  748. struct clk_local *t = &clk_local_tbl[id];
  749. void *ns_reg = REG(t->ns_reg);
  750. uint32_t reg_val = 0;
  751.  
  752. reg_val = readl(ns_reg);
  753. if (t->type == MND) {
  754. /* mode can be either 0 or 1. So the R-value of the
  755. * expression will evaluate to MNCNTR_EN_MASK or 0. This
  756. * avoids the need for a "if(mode == 1)". A "&" will not work
  757. * here. */
  758. reg_val |= (MNCNTR_EN_MASK * t->current_freq->mode);
  759. writel(reg_val, ns_reg);
  760. }
  761. if (t->root_en_mask) {
  762. reg_val |= t->root_en_mask;
  763. writel(reg_val, ns_reg);
  764. }
  765. if (t->br_en_mask) {
  766. reg_val |= t->br_en_mask;
  767. writel(reg_val, ns_reg);
  768. }
  769. return 0;
  770. }
  771.  
  772. static void _soc_clk_disable(unsigned id)
  773. {
  774. struct clk_local *t = &clk_local_tbl[id];
  775. void *ns_reg = REG(t->ns_reg);
  776. uint32_t reg_val = 0;
  777.  
  778. reg_val = readl(ns_reg);
  779.  
  780. if (t->br_en_mask) {
  781. reg_val &= ~(t->br_en_mask);
  782. writel(reg_val, ns_reg);
  783. }
  784. if (t->root_en_mask) {
  785. reg_val &= ~(t->root_en_mask);
  786. writel(reg_val, ns_reg);
  787. }
  788. if (t->type == MND) {
  789. reg_val &= ~MNCNTR_EN_MASK;
  790. writel(reg_val, ns_reg);
  791. }
  792. }
  793.  
  794. static int soc_clk_enable_nolock(unsigned id)
  795. {
  796. struct clk_local *t = &clk_local_tbl[id];
  797. int ret = 0;
  798.  
  799. if (!t->count) {
  800. ret = vote_msmc1(t->current_freq->msmc1);
  801. if (ret)
  802. return ret;
  803. if (t->parent != C(NONE)) {
  804. ret = soc_clk_enable_nolock(t->parent);
  805. if (ret)
  806. return ret;
  807. }
  808. src_enable(t->current_freq->src);
  809. ret = _soc_clk_enable(id);
  810. }
  811. t->count++;
  812.  
  813. return ret;
  814. }
  815.  
  816. static void soc_clk_disable_nolock(unsigned id)
  817. {
  818. struct clk_local *t = &clk_local_tbl[id];
  819.  
  820. if (!t->count) {
  821. pr_warning("Reference count mismatch in clock disable!\n");
  822. return;
  823. }
  824. if (t->count)
  825. t->count--;
  826. if (t->count == 0) {
  827. _soc_clk_disable(id);
  828. src_disable(t->current_freq->src);
  829. unvote_msmc1(t->current_freq->msmc1);
  830. if (t->parent != C(NONE))
  831. soc_clk_disable_nolock(t->parent);
  832. }
  833.  
  834. return;
  835. }
  836.  
  837. static int update_pwr_rail(unsigned id, int enable)
  838. {
  839. int pwr_id = 0;
  840. switch (id) {
  841. case C(AXI_ROTATOR):
  842. pwr_id = PWR_RAIL_ROTATOR_CLK;
  843. break;
  844. case C(GRP_2D):
  845. pwr_id = PWR_RAIL_GRP_2D_CLK;
  846. break;
  847. case C(GRP_3D):
  848. pwr_id = PWR_RAIL_GRP_CLK;
  849. break;
  850. case C(MFC):
  851. pwr_id = PWR_RAIL_MFC_CLK;
  852. break;
  853. case C(VFE):
  854. pwr_id = PWR_RAIL_VFE_CLK;
  855. break;
  856. case C(VPE):
  857. pwr_id = PWR_RAIL_VPE_CLK;
  858. break;
  859. default:
  860. return 0;
  861. }
  862.  
  863. return internal_pwr_rail_ctl_auto(pwr_id, enable);
  864. }
  865.  
  866. static int soc_clk_enable(unsigned id)
  867. {
  868. int ret = 0;
  869. unsigned long flags;
  870.  
  871. spin_lock_irqsave(&clock_reg_lock, flags);
  872. ret = soc_clk_enable_nolock(id);
  873. if (ret)
  874. goto unlock;
  875. /*
  876. * The modem might modify the register bits for the clock branch when
  877. * the rail is enabled/disabled, so enable the rail inside the lock
  878. * instead of outside it.
  879. */
  880. ret = update_pwr_rail(id, 1);
  881. if (ret)
  882. soc_clk_disable_nolock(id);
  883. unlock:
  884. spin_unlock_irqrestore(&clock_reg_lock, flags);
  885.  
  886. return ret;
  887. }
  888.  
  889. static void soc_clk_disable(unsigned id)
  890. {
  891. unsigned long flags;
  892.  
  893. spin_lock_irqsave(&clock_reg_lock, flags);
  894. update_pwr_rail(id, 0);
  895. soc_clk_disable_nolock(id);
  896. spin_unlock_irqrestore(&clock_reg_lock, flags);
  897. }
  898.  
  899. static void soc_clk_auto_off(unsigned id)
  900. {
  901. unsigned long flags;
  902.  
  903. spin_lock_irqsave(&clock_reg_lock, flags);
  904. _soc_clk_disable(id);
  905. spin_unlock_irqrestore(&clock_reg_lock, flags);
  906. }
  907.  
  908. static long soc_clk_round_rate(unsigned id, unsigned rate)
  909. {
  910. struct clk_local *t = &clk_local_tbl[id];
  911. struct clk_freq_tbl *f;
  912.  
  913. if (t->type != MND && t->type != BASIC)
  914. return -EINVAL;
  915.  
  916. for (f = t->freq_tbl; f->freq_hz != FREQ_END; f++)
  917. if (f->freq_hz >= rate)
  918. return f->freq_hz;
  919.  
  920. return -EPERM;
  921. }
  922.  
  923. static int soc_clk_set_rate(unsigned id, unsigned rate)
  924. {
  925. struct clk_local *t = &clk_local_tbl[id];
  926. struct clk_freq_tbl *cf = t->current_freq;
  927. struct clk_freq_tbl *nf;
  928. uint32_t *chld = t->children;
  929. void *ns_reg = REG(t->ns_reg);
  930. void *md_reg = REG(t->md_reg);
  931. uint32_t reg_val = 0;
  932. int i, ret = 0;
  933. unsigned long flags;
  934. long rounded;
  935.  
  936. rounded = soc_clk_round_rate(id, rate);
  937. if (rounded != rate)
  938. pr_warning("Use clk_round_rate() before clk_set_rate() with "
  939. "clock %u\n", id);
  940. rate = rounded;
  941.  
  942. if (t->type != MND && t->type != BASIC)
  943. return -EPERM;
  944.  
  945. spin_lock_irqsave(&clock_reg_lock, flags);
  946.  
  947. if (rate == cf->freq_hz)
  948. goto release_lock;
  949.  
  950. for (nf = t->freq_tbl; nf->freq_hz != FREQ_END; nf++)
  951. if (nf->freq_hz == rate)
  952. break;
  953.  
  954. if (nf->freq_hz == FREQ_END) {
  955. ret = -EINVAL;
  956. goto release_lock;
  957. }
  958.  
  959. if (t->freq_mask == 0) {
  960. t->current_freq = nf;
  961. goto release_lock;
  962. }
  963.  
  964. /* Disable all branches before changing rate to prevent jitter. */
  965. for (i = 0; chld && chld[i] != C(NONE); i++) {
  966. struct clk_local *ch = &clk_local_tbl[chld[i]];
  967. /* Don't bother turning off if it is already off.
  968. * Checking ch->count is cheaper (cache) than reading and
  969. * writing to a register (uncached/unbuffered). */
  970. if (ch->count) {
  971. reg_val = readl(REG(ch->ns_reg));
  972. reg_val &= ~(ch->br_en_mask);
  973. writel(reg_val, REG(ch->ns_reg));
  974. }
  975. }
  976.  
  977. if (t->count) {
  978. _soc_clk_disable(id);
  979.  
  980. ret = vote_msmc1(nf->msmc1);
  981. if (ret)
  982. goto msmc1_err;
  983. /* Turn on PLL of the new freq. */
  984. src_enable(nf->src);
  985. }
  986.  
  987. /* Some clocks share the same register, so must be careful when
  988. * assuming a register doesn't need to be re-read. */
  989. reg_val = readl(ns_reg);
  990. if (t->type == MND) {
  991. reg_val |= MNCNTR_RST_MASK;
  992. writel(reg_val, ns_reg);
  993. /* TODO: Currently writing 0's into reserved bits for 8-bit
  994. * MND. Can be avoided by adding md_mask. */
  995. if (nf->mode)
  996. writel(nf->md_val, md_reg);
  997. reg_val &= ~MNCNTR_MODE_MASK;
  998. reg_val |= (MNCNTR_MODE * nf->mode);
  999. }
  1000. reg_val &= ~(t->freq_mask);
  1001. reg_val |= nf->ns_val;
  1002. writel(reg_val, ns_reg);
  1003.  
  1004. if (t->type == MND) {
  1005. reg_val &= ~MNCNTR_RST_MASK;
  1006. writel(reg_val, ns_reg);
  1007. }
  1008.  
  1009. if (t->count) {
  1010. /* Turn off PLL of the old freq. */
  1011. src_disable(cf->src);
  1012. unvote_msmc1(cf->msmc1);
  1013. }
  1014.  
  1015. /* Current freq must be updated before _soc_clk_enable() is called to
  1016. * make sure the MNCNTR_E bit is set correctly. */
  1017. t->current_freq = nf;
  1018.  
  1019. msmc1_err:
  1020. if (t->count)
  1021. _soc_clk_enable(id);
  1022. /* Enable only branches that were ON before. */
  1023. for (i = 0; chld && chld[i] != C(NONE); i++) {
  1024. struct clk_local *ch = &clk_local_tbl[chld[i]];
  1025. if (ch->count) {
  1026. reg_val = readl(REG(ch->ns_reg));
  1027. reg_val |= ch->br_en_mask;
  1028. writel(reg_val, REG(ch->ns_reg));
  1029. }
  1030. }
  1031.  
  1032. release_lock:
  1033. spin_unlock_irqrestore(&clock_reg_lock, flags);
  1034. return ret;
  1035. }
  1036.  
  1037. static int soc_clk_set_min_rate(unsigned id, unsigned rate)
  1038. {
  1039. long rounded = soc_clk_round_rate(id, rate);
  1040. return soc_clk_set_rate(id, rounded);
  1041. }
  1042.  
  1043. static int soc_clk_set_max_rate(unsigned id, unsigned rate)
  1044. {
  1045. return -EPERM;
  1046. }
  1047.  
  1048. static int soc_clk_set_flags(unsigned id, unsigned clk_flags)
  1049. {
  1050. uint32_t regval, ret = 0;
  1051. unsigned long flags;
  1052.  
  1053. spin_lock_irqsave(&clock_reg_lock, flags);
  1054. switch (id) {
  1055. case C(VFE):
  1056. regval = readl(REG(CAM_VFE_NS));
  1057. /* Flag values chosen for backward compatibility
  1058. * with proc_comm remote clock control. */
  1059. if (clk_flags == 0x00000100) {
  1060. /* Select external source. */
  1061. regval |= B(14);
  1062. } else if (clk_flags == 0x00000200) {
  1063. /* Select internal source. */
  1064. regval &= ~B(14);
  1065. } else
  1066. ret = -EINVAL;
  1067.  
  1068. writel(regval, REG(CAM_VFE_NS));
  1069. break;
  1070. default:
  1071. ret = -EPERM;
  1072. }
  1073. spin_unlock_irqrestore(&clock_reg_lock, flags);
  1074.  
  1075. return ret;
  1076. }
  1077.  
  1078. static unsigned soc_clk_get_rate(unsigned id)
  1079. {
  1080. struct clk_local *t = &clk_local_tbl[id];
  1081. unsigned long flags;
  1082. unsigned ret = 0;
  1083.  
  1084. if (t->type == NORATE)
  1085. return -EINVAL;
  1086.  
  1087. spin_lock_irqsave(&clock_reg_lock, flags);
  1088. ret = t->current_freq->freq_hz;
  1089. spin_unlock_irqrestore(&clock_reg_lock, flags);
  1090.  
  1091. /* Return 0 if the rate has never been set. Might not be correct,
  1092. * but it's good enough. */
  1093. if (ret == FREQ_END)
  1094. ret = 0;
  1095.  
  1096. return ret;
  1097. }
  1098.  
  1099. static unsigned soc_clk_is_enabled(unsigned id)
  1100. {
  1101. return !!(clk_local_tbl[id].count);
  1102. }
  1103.  
  1104. struct clk_ops clk_ops_7x30 = {
  1105. .enable = soc_clk_enable,
  1106. .disable = soc_clk_disable,
  1107. .auto_off = soc_clk_auto_off,
  1108. .reset = NULL, /* Uses proc_comm */
  1109. .set_rate = soc_clk_set_rate,
  1110. .set_min_rate = soc_clk_set_min_rate,
  1111. .set_max_rate = soc_clk_set_max_rate,
  1112. .set_flags = soc_clk_set_flags,
  1113. .get_rate = soc_clk_get_rate,
  1114. .is_enabled = soc_clk_is_enabled,
  1115. .round_rate = soc_clk_round_rate,
  1116. };
  1117.  
  1118. enum {
  1119. SH2_OWN_GLBL,
  1120. SH2_OWN_APPS1,
  1121. SH2_OWN_APPS2,
  1122. SH2_OWN_ROW1,
  1123. SH2_OWN_ROW2,
  1124. SH2_OWN_APPS3,
  1125. NUM_OWNERSHIP
  1126. };
  1127. static __initdata uint32_t ownership_regs[NUM_OWNERSHIP];
  1128.  
  1129. static void __init cache_ownership(void)
  1130. {
  1131. ownership_regs[SH2_OWN_GLBL] = readl(REG_BASE(SH2_OWN_GLBL_REG));
  1132. ownership_regs[SH2_OWN_APPS1] = readl(REG_BASE(SH2_OWN_APPS1_REG));
  1133. ownership_regs[SH2_OWN_APPS2] = readl(REG_BASE(SH2_OWN_APPS2_REG));
  1134. ownership_regs[SH2_OWN_ROW1] = readl(REG_BASE(SH2_OWN_ROW1_REG));
  1135. ownership_regs[SH2_OWN_ROW2] = readl(REG_BASE(SH2_OWN_ROW2_REG));
  1136. ownership_regs[SH2_OWN_APPS3] = readl(REG_BASE(SH2_OWN_APPS3_REG));
  1137. }
  1138.  
  1139. static void __init print_ownership(void)
  1140. {
  1141. pr_info("Clock ownership\n");
  1142. pr_info(" GLBL : %08x\n", ownership_regs[SH2_OWN_GLBL]);
  1143. pr_info(" APPS : %08x %08x %08x\n", ownership_regs[SH2_OWN_APPS1],
  1144. ownership_regs[SH2_OWN_APPS2], ownership_regs[SH2_OWN_APPS3]);
  1145. pr_info(" ROW : %08x %08x\n", ownership_regs[SH2_OWN_ROW1],
  1146. ownership_regs[SH2_OWN_ROW2]);
  1147. }
  1148.  
  1149. /*
  1150. * This is a many-to-one mapping since we don't know how the remote clock code
  1151. * has decided to handle the dependencies between clocks for a particular
  1152. * hardware block. We determine the ownership for all the clocks on a block by
  1153. * checking the ownership bit of one register (usually the ns register).
  1154. */
  1155. #define O(x) &ownership_regs[x]
  1156. static struct clk_local_ownership {
  1157. uint32_t *reg;
  1158. uint32_t bit;
  1159. } ownership_map[] __initdata = {
  1160. [C(GRP_2D)] = { O(SH2_OWN_APPS1), B(6) },
  1161. [C(GRP_2D_P)] = { O(SH2_OWN_APPS1), B(6) },
  1162. [C(HDMI)] = { O(SH2_OWN_APPS1), B(31) },
  1163. [C(JPEG)] = { O(SH2_OWN_APPS1), B(0) },
  1164. [C(JPEG_P)] = { O(SH2_OWN_APPS1), B(0) },
  1165. [C(LPA_CODEC)] = { O(SH2_OWN_APPS1), B(23) },
  1166. [C(LPA_CORE)] = { O(SH2_OWN_APPS1), B(23) },
  1167. [C(LPA_P)] = { O(SH2_OWN_APPS1), B(23) },
  1168. [C(MI2S_CODEC_RX_M)] = { O(SH2_OWN_APPS1), B(12) },
  1169. [C(MI2S_CODEC_RX_S)] = { O(SH2_OWN_APPS1), B(12) },
  1170. [C(MI2S_CODEC_TX_M)] = { O(SH2_OWN_APPS1), B(14) },
  1171. [C(MI2S_CODEC_TX_S)] = { O(SH2_OWN_APPS1), B(14) },
  1172. [C(MIDI)] = { O(SH2_OWN_APPS1), B(22) },
  1173. [C(SDAC)] = { O(SH2_OWN_APPS1), B(26) },
  1174. [C(VFE)] = { O(SH2_OWN_APPS1), B(8) },
  1175. [C(VFE_CAMIF)] = { O(SH2_OWN_APPS1), B(8) },
  1176. [C(VFE_MDC)] = { O(SH2_OWN_APPS1), B(8) },
  1177. [C(VFE_P)] = { O(SH2_OWN_APPS1), B(8) },
  1178.  
  1179. [C(GRP_3D)] = { O(SH2_OWN_APPS2), B(0) },
  1180. [C(GRP_3D_P)] = { O(SH2_OWN_APPS2), B(0) },
  1181. [C(GRP_3D_SRC)] = { O(SH2_OWN_APPS2), B(0) },
  1182. [C(IMEM)] = { O(SH2_OWN_APPS2), B(0) },
  1183. [C(MDP_LCDC_PAD_PCLK)] = { O(SH2_OWN_APPS2), B(4) },
  1184. [C(MDP_LCDC_PCLK)] = { O(SH2_OWN_APPS2), B(4) },
  1185. [C(MDP_P)] = { O(SH2_OWN_APPS2), B(4) },
  1186. [C(MDP_VSYNC)] = { O(SH2_OWN_APPS2), B(28) },
  1187. [C(TSIF_REF)] = { O(SH2_OWN_APPS2), B(5) },
  1188. [C(TSIF_P)] = { O(SH2_OWN_APPS2), B(5) },
  1189. [C(TV)] = { O(SH2_OWN_APPS2), B(2) },
  1190. [C(TV_DAC)] = { O(SH2_OWN_APPS2), B(2) },
  1191. [C(TV_ENC)] = { O(SH2_OWN_APPS2), B(2) },
  1192.  
  1193. [C(EMDH)] = { O(SH2_OWN_ROW1), B(7) },
  1194. [C(EMDH_P)] = { O(SH2_OWN_ROW1), B(7) },
  1195. [C(I2C)] = { O(SH2_OWN_ROW1), B(11) },
  1196. [C(I2C_2)] = { O(SH2_OWN_ROW1), B(12) },
  1197. [C(MDC)] = { O(SH2_OWN_ROW1), B(17) },
  1198. [C(PMDH)] = { O(SH2_OWN_ROW1), B(19) },
  1199. [C(PMDH_P)] = { O(SH2_OWN_ROW1), B(19) },
  1200. [C(SDC1)] = { O(SH2_OWN_ROW1), B(23) },
  1201. [C(SDC1_P)] = { O(SH2_OWN_ROW1), B(23) },
  1202. [C(SDC2)] = { O(SH2_OWN_ROW1), B(25) },
  1203. [C(SDC2_P)] = { O(SH2_OWN_ROW1), B(25) },
  1204. [C(SDC3)] = { O(SH2_OWN_ROW1), B(27) },
  1205. [C(SDC3_P)] = { O(SH2_OWN_ROW1), B(27) },
  1206. [C(SDC4)] = { O(SH2_OWN_ROW1), B(29) },
  1207. [C(SDC4_P)] = { O(SH2_OWN_ROW1), B(29) },
  1208. [C(UART2)] = { O(SH2_OWN_ROW1), B(0) },
  1209. [C(USB_HS2)] = { O(SH2_OWN_ROW1), B(2) },
  1210. [C(USB_HS2_CORE)] = { O(SH2_OWN_ROW1), B(2) },
  1211. [C(USB_HS2_P)] = { O(SH2_OWN_ROW1), B(2) },
  1212. [C(USB_HS3)] = { O(SH2_OWN_ROW1), B(4) },
  1213. [C(USB_HS3_CORE)] = { O(SH2_OWN_ROW1), B(4) },
  1214. [C(USB_HS3_P)] = { O(SH2_OWN_ROW1), B(4) },
  1215.  
  1216. [C(QUP_I2C)] = { O(SH2_OWN_ROW2), B(3) },
  1217. [C(SPI)] = { O(SH2_OWN_ROW2), B(1) },
  1218. [C(SPI_P)] = { O(SH2_OWN_ROW2), B(1) },
  1219. [C(UART1)] = { O(SH2_OWN_ROW2), B(9) },
  1220. [C(UART1DM)] = { O(SH2_OWN_ROW2), B(6) },
  1221. [C(UART1DM_P)] = { O(SH2_OWN_ROW2), B(6) },
  1222. [C(UART2DM)] = { O(SH2_OWN_ROW2), B(8) },
  1223. [C(UART2DM_P)] = { O(SH2_OWN_ROW2), B(8) },
  1224. [C(USB_HS)] = { O(SH2_OWN_ROW2), B(11) },
  1225. [C(USB_HS_CORE)] = { O(SH2_OWN_ROW2), B(11) },
  1226. [C(USB_HS_SRC)] = { O(SH2_OWN_ROW2), B(11) },
  1227. [C(USB_HS_P)] = { O(SH2_OWN_ROW2), B(11) },
  1228.  
  1229. [C(CAM_M)] = { O(SH2_OWN_APPS3), B(6) },
  1230. [C(CAMIF_PAD_P)] = { O(SH2_OWN_APPS3), B(6) },
  1231. [C(CSI0)] = { O(SH2_OWN_APPS3), B(11) },
  1232. [C(CSI0_VFE)] = { O(SH2_OWN_APPS3), B(11) },
  1233. [C(CSI0_P)] = { O(SH2_OWN_APPS3), B(11) },
  1234. [C(MDP)] = { O(SH2_OWN_APPS3), B(0) },
  1235. [C(MFC)] = { O(SH2_OWN_APPS3), B(2) },
  1236. [C(MFC_DIV2)] = { O(SH2_OWN_APPS3), B(2) },
  1237. [C(MFC_P)] = { O(SH2_OWN_APPS3), B(2) },
  1238. [C(VPE)] = { O(SH2_OWN_APPS3), B(4) },
  1239.  
  1240. [C(ADM)] = { O(SH2_OWN_GLBL), B(8) },
  1241. [C(AXI_ROTATOR)] = { O(SH2_OWN_GLBL), B(13) },
  1242. [C(ROTATOR_IMEM)] = { O(SH2_OWN_GLBL), B(13) },
  1243. [C(ROTATOR_P)] = { O(SH2_OWN_GLBL), B(13) },
  1244. };
  1245.  
  1246. struct clk_ops * __init clk_7x30_is_local(uint32_t id)
  1247. {
  1248. uint32_t local, bit = ownership_map[id].bit;
  1249. uint32_t *reg = ownership_map[id].reg;
  1250.  
  1251. BUG_ON(id >= ARRAY_SIZE(ownership_map) || !reg);
  1252.  
  1253. local = *reg & bit;
  1254. return local ? &clk_ops_7x30 : NULL;
  1255. }
  1256.  
  1257. static struct reg_init {
  1258. void *reg;
  1259. uint32_t mask;
  1260. uint32_t val;
  1261. } ri_list[] __initdata = {
  1262. /* Enable UMDX_P clock. Known to causes issues, so never turn off. */
  1263. {REG(GLBL_CLK_ENA_2_SC), B(2), B(2)},
  1264.  
  1265. {REG(EMDH_NS), BM(18, 17) , BVAL(18, 17, 0x3)}, /* RX div = div-4. */
  1266. {REG(PMDH_NS), BM(18, 17), BVAL(18, 17, 0x3)}, /* RX div = div-4. */
  1267. /* MI2S_CODEC_RX_S src = MI2S_CODEC_RX_M. */
  1268. {REG(MI2S_RX_NS), B(14), 0x0},
  1269. /* MI2S_CODEC_TX_S src = MI2S_CODEC_TX_M. */
  1270. {REG(MI2S_TX_NS), B(14), 0x0},
  1271. {REG(MI2S_NS), B(14), 0x0}, /* MI2S_S src = MI2S_M. */
  1272. /* Allow DSP to decide the LPA CORE src. */
  1273. {REG(LPA_CORE_CLK_MA0), B(0), B(0)},
  1274. {REG(LPA_CORE_CLK_MA2), B(0), B(0)},
  1275. {REG(0x02EC), 0xF, 0xD}, /* MI2S_CODEC_RX_S div = div-8. */
  1276. {REG(0x02F0), 0xF, 0xD}, /* MI2S_CODEC_TX_S div = div-8. */
  1277. {REG(0x02E4), 0xF, 0x3}, /* MI2S_S div = div-4. */
  1278. {REG(MDC_NS), 0x3, 0x3}, /* MDC src = external MDH src. */
  1279. {REG(SDAC_NS), BM(15, 14), 0x0}, /* SDAC div = div-1. */
  1280. /* Disable sources TCXO/5 & TCXO/6. UART1 src = TCXO*/
  1281. {REG(UART_NS), BM(26, 25) | BM(2, 0), 0x0},
  1282. {REG(MDP_VSYNC_REG), 0xC, 0x4}, /* MDP VSYNC src = LPXO. */
  1283. /* HDMI div = div-1, non-inverted. tv_enc_src = tv_clk_src */
  1284. {REG(HDMI_NS), 0x7, 0x0},
  1285. {REG(TV_NS), BM(15, 14), 0x0}, /* tv_clk_src_div2 = div-1 */
  1286.  
  1287. /* USBH core clocks src = USB_HS_SRC. */
  1288. {REG(USBH_NS), B(15), B(15)},
  1289. {REG(USBH2_NS), B(6), B(6)},
  1290. {REG(USBH3_NS), B(6), B(6)},
  1291. };
  1292.  
  1293. #define set_1rate(clk) \
  1294. soc_clk_set_rate(C(clk), clk_local_tbl[C(clk)].freq_tbl->freq_hz)
  1295. __init int clk_7x30_init(void)
  1296. {
  1297. int i;
  1298. uint32_t val;
  1299.  
  1300. cache_ownership();
  1301. print_ownership();
  1302.  
  1303. /* When we have no local clock control, the rest of the code in this
  1304. * function is a NOP since writes to shadow regions that we don't own
  1305. * are ignored. */
  1306.  
  1307. /* Disable all the child clocks of USB_HS_SRC. This needs to be done
  1308. * before the register init loop since it changes the source of the
  1309. * USB HS core clocks. */
  1310. for (i = 0; chld_usb_src[i] != C(NONE); i++)
  1311. _soc_clk_disable(chld_usb_src[i]);
  1312.  
  1313. soc_clk_set_rate(C(USB_HS_SRC), clk_tbl_usb[0].freq_hz);
  1314.  
  1315. for (i = 0; i < ARRAY_SIZE(ri_list); i++) {
  1316. val = readl(ri_list[i].reg);
  1317. val &= ~ri_list[i].mask;
  1318. val |= ri_list[i].val;
  1319. writel(val, ri_list[i].reg);
  1320. }
  1321.  
  1322. /* This is just to update the driver data structures. The actual
  1323. * register set up is taken care of in the register init loop
  1324. * or is the default value out of reset. */
  1325. set_1rate(I2C);
  1326. set_1rate(I2C_2);
  1327. set_1rate(QUP_I2C);
  1328. set_1rate(UART1);
  1329. set_1rate(UART2);
  1330. set_1rate(LPA_CODEC);
  1331.  
  1332. return 0;
  1333. }
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