sliq19882

Musebook Oreboot DRAM init

Aug 10th, 2024
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  1. sys: 0x1200
  2. bm:2
  3. ROM: usb download handler
  4. usb2d_initialize : enter
  5. Controller Run
  6. usb rst int
  7. SETUP: 0x80 0x6 0x100
  8. usb rst int
  9. SETUP: 0x0 0x5 0x31
  10. SETUP: 0x80 0x6 0x100
  11. SETUP: 0x80 0x6 0x200
  12. SETUP: 0x80 0x6 0x200
  13. SETUP: 0x80 0x6 0x300
  14. SETUP: 0x80 0x6 0x302
  15. SETUP: 0x80 0x6 0x301
  16. SETUP: 0x80 0x6 0x30a
  17. SETUP: 0x0 0x9 0x1
  18. usb_rx_bytes : len= 4096 pBuf= 0xc0838720
  19. SETUP: 0x80 0x6 0x302
  20. SETUP: 0x80 0x6 0x304
  21. fastboot_handle_command: max-download-size
  22. usb_tx_bytes : len= 65 pBuf= 0xc083fe88
  23. usb_rx_bytes : len= 4096 pBuf= 0xc0838720
  24. fastboot_handle_command: 00008cc0
  25. Starting download of 36032 bytes
  26. usb_tx_bytes : len= 65 pBuf= 0xc083fe88
  27. usb_rx_bytes : len= 36032 pBuf= 0xc0800000
  28. usb_tx_bytes : len= 65 pBuf= 0xc083fe88
  29. usb_rx_bytes : len= 4096 pBuf= 0xc0838720
  30. fastboot_handle_command: continue
  31. usb_tx_bytes : len= 65 pBuf= 0xc083fe88
  32. j...
  33. oreboot ð bt0
  34. RISC-V arch 8000000058000001
  35. RISC-V core vendor: SpacemiT (0x0710)
  36. RISC-V implementation: X60 (0x1000000049772200)
  37. RISC-V hart ID 0
  38. Boot mode: 0xc08381a0
  39. Boot entry: 0xffe03b36
  40. HeaderInfo {
  41. magic: 0x6ded1e0,
  42. crc32: 0xc23e034a,
  43. chipid: 0x9bb6cc1b8baeb641,
  44. mac_addr: 0xaeba42965924c6c9,
  45. version: 0x3691b684,
  46. cs_num: 0xb56abde1,
  47. }
  48. dump 1024 bytes @c0800000
  49. e0d1de064a033ec241b6ae8b1bccb69bc9c624599642baae84b69136e1bd6ab5
  50. 14333f67d54c698202db5bed4fce294aef31f0c44d6db9e490c3577f606d3821
  51. a4f0e0ba5793715641938afc43a1adc23d3e945629b111c817037cec782476ec
  52. d4a3be098fb5cb75d4191c2d6b87fe2e10593975ba5739c37345d04d47b98ff2
  53. 14cdbdc2fff228183c0c9a9b2099766740719c70cd018b7b30503e01fdd6dd40
  54. db66d04e65f9f9a9e1f08edead41df8d84556dc989ec7f4e82b9198cf5eec9ef
  55. 7913086b2bfff2855a6525fac8cfed30a89b6a69c951276fc2c7a412118fac42
  56. 8c7bd55f0dbed9230717a3538a920ee32fa189a6ea79956a702e391916745007
  57. 414948440100000000020000000000000001000000000000a5a5a5a5a5a5a5a5
  58. 000000000200000073706c000000000000000000000000000000000000000000
  59. 0000000000000000000000000000000000000000000000000000000000000000
  60. 0000000000000000000000000000000000000000000000000000000000000000
  61. 0000000000000000000000000000000000000000000000000000000000000000
  62. 0000000000000000000000000000000000000000000000000000000000000000
  63. 0000000000000000000000000000000000000000000000000000000000000000
  64. 0000000000000000000000000000000000000000000000000000000000000000
  65. 0000000000000000000000000000000000000000000000000000000000000000
  66. 0000000000000000000000000000000000000000000000000000000000000000
  67. 0000000000000000000000000000000000000000000000000000000000000000
  68. 0000000000000000000000000000000000000000000000000000000000000000
  69. 0000000000000000000000000000000000000000000000000000000000000000
  70. 0000000000000000000000000000000000000000000000000000000000000000
  71. 0000000000000000000000000000000000000000000000000000000000000000
  72. 0000000000000000000000000000000000000000000000000000000000000000
  73. d263462f1b7be1bbc2a160f5ece41575781d7120b3c95101927eca04e9d5c47e
  74. c8639b0d530a14ceada30910d9add7b04739c7d7dcba696ae1efff835e53ec40
  75. fd50f916c7d2d6c9c004388fb574e38eef23ae58eb591fad0aff47a4c82720b5
  76. eb0649b58b5a664db8a088ad6a9a3f88951618380e9b2a9368f9449a0c3b9227
  77. 3cb179c42baaa309375797cd2894a341b557b7fcdef90ede70a7b5b7abac917f
  78. 1dec10dfe100426ebc1571062c154934856acc84f38f6dae0d66a436e25be1db
  79. f819a9193c07a8a594a4d667a16d8397a4203705502929fadd603f9f63f864da
  80. 8d2dedf8fee3cb4c330137fcca99e6cbf8e6eebced7fe3dcf42e5fd99dbaab3d
  81. ADDR[0xc0000304]=0x00800400
  82. PHY INIT done
  83. wait DRAM INIT
  84. DRAM INIT done
  85. DRAM Mode register Init done.
  86. DDR size (density): 16384MB
  87. MR 8: 88
  88. DEBUG-ADDR[0xc0000200]:0x00110001
  89. DEBUG-ADDR[0xc0000204]:0x00000000
  90. DEBUG-ADDR[0xc0000208]:0x00110001
  91. DEBUG-ADDR[0xc000020c]:0x00000002
  92. DEBUG-ADDR[0xc0000220]:0x05030832
  93. DEBUG-ADDR[0xc0000224]:0x05030832
  94. self refresh start
  95. self refresh done
  96. Training start...
  97. Training init...
  98. Dump margin and setting before training...
  99. write leveling
  100. read gate train
  101. read gate training pass
  102. read gate training pass
  103. 0xc0040070 = 0x00017474
  104. 0xc0040170 = 0x00017575
  105. 0xc0041070 = 0x00017070
  106. 0xc0041170 = 0x00016f6f
  107. read training
  108. each RX Vref corresponding min margin
  109. 00: 22, 01: 23, 02: 23, 03: 24,
  110. 04: 24, 05: 24, 06: 24, 07: 24,
  111. 08: 23, 09: 23, 10: 22, 11: 22,
  112. 12: 21, 13: 18, 14: 16, 15: 15,
  113. optimize RX Vref adjust = 3, corresponding best margin = 24
  114. Optimize fine RX vref step: 3
  115. write training
  116. each TX Vref corresponding min margin
  117. 00: 24, 01: 24, 02: 24, 03: 24,
  118. 04: 24, 05: 24, 06: 24, 07: 24,
  119. 08: 24, 09: 24, 10: 24, 11: 24,
  120. 12: 24, 13: 24, 14: 24, 15: 24,
  121. optimize TX Vref adjust = 21, corresponding best margin = 33
  122. Optimize fine TX vref step: 21
  123. Training status [0xc0058000]=0x00000000
  124. change to 1600
  125. frequency change done!
  126. self refresh start
  127. self refresh done
  128. Training start...
  129. Training init...
  130. Dump margin and setting before training...
  131. write leveling
  132. read gate train
  133. read gate training pass
  134. read gate training pass
  135. 0xc0044070 = 0x00016060
  136. 0xc0044170 = 0x00016161
  137. 0xc0045070 = 0x00015c5c
  138. 0xc0045170 = 0x00015b5b
  139. read training
  140. each RX Vref corresponding min margin
  141. 00: 15, 01: 16, 02: 16, 03: 17,
  142. 04: 18, 05: 18, 06: 18, 07: 17,
  143. 08: 16, 09: 16, 10: 15, 11: 15,
  144. 12: 14, 13: 10, 14: 09, 15: 07,
  145. optimize RX Vref adjust = 4, corresponding best margin = 18
  146. Optimize fine RX vref step: 4
  147. write training
  148. each TX Vref corresponding min margin
  149. 00: 17, 01: 17, 02: 17, 03: 17,
  150. 04: 17, 05: 17, 06: 17, 07: 17,
  151. 08: 17, 09: 17, 10: 17, 11: 17,
  152. 12: 17, 13: 17, 14: 17, 15: 17,
  153. optimize TX Vref adjust = 21, corresponding best margin = 33
  154. Optimize fine TX vref step: 21
  155. Training status [0xc0058000]=0x00000000
  156. change to 2400
  157. frequency change done!
  158. self refresh start
  159. self refresh done
  160. Training start...
  161. Training init...
  162. Dump margin and setting before training...
  163. write leveling
  164. read gate train
  165. read gate training pass
  166. read gate training pass
  167. 0xc0048070 = 0x00014e4e
  168. 0xc0048170 = 0x00014d4d
  169. 0xc0049070 = 0x00014a4a
  170. 0xc0049170 = 0x00014949
  171. read training
  172. each RX Vref corresponding min margin
  173. 00: 08, 01: 09, 02: 09, 03: 09,
  174. 04: 09, 05: 10, 06: 09, 07: 09,
  175. 08: 09, 09: 08, 10: 07, 11: 06,
  176. 12: 06, 13: 00, 14: 00, 15: 00,
  177. optimize RX Vref adjust = 5, corresponding best margin = 10
  178. Optimize fine RX vref step: 5
  179. write training
  180. each TX Vref corresponding min margin
  181. 00: 10, 01: 10, 02: 10, 03: 10,
  182. 04: 10, 05: 10, 06: 10, 07: 10,
  183. 08: 10, 09: 10, 10: 10, 11: 10,
  184. 12: 10, 13: 10, 14: 10, 15: 10,
  185. optimize TX Vref adjust = 21, corresponding best margin = 35
  186. Optimize fine TX vref step: 21
  187. Training status [0xc0058000]=0x00000000
  188. change to 2400
  189. frequency change done!
  190. DRAM test: write patterns...
  191. DRAM test: reading back...
  192. DRAM test: done :)
  193. „
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