Lab5

module Lab5(
                input signed[7:0] SW,
                input [3:0]KEY,
                output reg [6:0] HEX0,
                output reg [6:0] HEX1,
                output reg [6:0] HEX2,
                output reg [6:0] HEX4,
                output reg [6:0] HEX5,
                output reg [6:0] HEX6

);


    reg signed[7:0] min, max;
    wire [6:0] h0,h1,h2,h4,h5,h6;

    hex_7seg seg0($signed(max[3:0]),h0);
    hex_7seg seg1($signed(max[6:4]),h1);
    hex_7seg seg2(max[7], h2);

    initial begin
        min = 0;
        max = 0;
        h0 = 7'b0;
        h1 = 7'b0;
        h2 = 7'b0;
        h4 = 7'b0;
        h5 = 7'b0;
        h6 = 7'b0;

    end

    always begin
        /*HEX0 = h0;
        HEX1 = h1;
        HEX2 = h2;
        HEX4 = h4;
        HEX5 = h5;
        HEX6 = h6;*/
    end
    always @(negedge KEY[0]) begin
        if(SW > max)
            max = SW;
        if(SW < min)
            min = SW;
    end

    always@(negedge KEY[1]) begin
        min = 0;
        max = 0;
        assign h0 = 7'b0;
        assign h1 = 7'b0;
        assign h2 = 7'b0;
        assign h4 = 7'b0;
        assign h5 = 7'b0;
        assign h6 = 7'b0;
    end
endmodule


module hex_7seg(hex_digit,seg);   //decimal to Hex converter

input [3:0] hex_digit;
output reg [6:0] seg;

always @ (hex_digit)
    case (hex_digit)
    4'h0: seg = 7'b1000000;
    4'h1: seg = 7'b1111001;
    4'h2: seg = 7'b0100100;
    4'h3: seg = 7'b0110000;
    4'h4: seg = 7'b0011001;
    4'h5: seg = 7'b0010010;
    4'h6: seg = 7'b0000010;
    4'h7: seg = 7'b1111000;
    4'h8: seg = 7'b0000000;
    4'h9: seg = 7'b0011000;
    4'ha: seg = 7'b0001000;
    4'hb: seg = 7'b0000011;
    4'hc: seg = 7'b1000110;
    4'hd: seg = 7'b0100001;
    4'he: seg = 7'b0000110;
    4'hf: seg = 7'b0001110;
    endcase

endmodule