mult_tb_clk.v

`include "mult_clk.v"
`timescale 1us/1us
module mult_tb;
   // on testbenches, inputs are regs
   reg[3:0] in1;
   reg[3:0] in2;
   reg clk;

   // on testbenches, outputs are wires
   wire[7:0] out;

   mult MULT1(in1,in2,clk, out);
   initial begin
      clk = 0;     in1 = 0;   in2 = 0;
      #(2*2**8) $finish;

   end // initial begin

   always  #1 clk = ~clk;
   always  #2 in1 = in1+1;
   always  #(2*2**4) in2 = in2+1;


   initial begin
      $monitor ("%t | in1 = %d | in2 = %d | clk = %d | out = %d", $time, in1, in2, clk, out);
      $dumpfile("dump.vcd");
      $dumpvars();
   end
endmodule // sr_tb