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3.18-rc1 utilite patch

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  1. diff --git a/arch/arm/boot/dts/imx6q-cm-fx6.dts b/arch/arm/boot/dts/imx6q-cm-fx6.dts
  2. index 99b46f8..831f398 100644
  3. --- a/arch/arm/boot/dts/imx6q-cm-fx6.dts
  4. +++ b/arch/arm/boot/dts/imx6q-cm-fx6.dts
  5. @@ -1,107 +1,809 @@
  6. /*
  7. - * Copyright 2013 CompuLab Ltd.
  8. - *
  9. - * Author: Valentin Raevsky <valentin@compulab.co.il>
  10. - *
  11. - * The code contained herein is licensed under the GNU General Public
  12. - * License. You may obtain a copy of the GNU General Public License
  13. - * Version 2 or later at the following locations:
  14. - *
  15. - * http://www.opensource.org/licenses/gpl-license.html
  16. - * http://www.gnu.org/copyleft/gpl.html
  17. - */
  18. -
  19. +* Copyright 2013 CompuLab Ltd.
  20. +*
  21. +* Author: Valentin Raevsky <valentin@compulab.co.il>
  22. +*
  23. +* The code contained herein is licensed under the GNU General Public
  24. +* License. You may obtain a copy of the GNU General Public License
  25. +* Version 2 or later at the following locations:
  26. +*
  27. +* http://www.opensource.org/licenses/gpl-license.html
  28. +* http://www.gnu.org/copyleft/gpl.html
  29. +*/
  30. +
  31. /dts-v1/;
  32. #include "imx6q.dtsi"
  33. -
  34. +#include <dt-bindings/sound/fsl-imx-audmux.h>
  35. / {
  36. - model = "CompuLab CM-FX6";
  37. - compatible = "compulab,cm-fx6", "fsl,imx6q";
  38. -
  39. - memory {
  40. - reg = <0x10000000 0x80000000>;
  41. - };
  42. -
  43. - leds {
  44. - compatible = "gpio-leds";
  45. -
  46. - heartbeat-led {
  47. - label = "Heartbeat";
  48. - gpios = <&gpio2 31 0>;
  49. - linux,default-trigger = "heartbeat";
  50. - };
  51. + model = "CompuLab CM-FX6";
  52. + compatible = "compulab,cm-fx6", "fsl,imx6q";
  53. +
  54. + memory {
  55. + reg = <0x10000000 0x80000000>;
  56. + };
  57. +
  58. + leds {
  59. + compatible = "gpio-leds";
  60. +
  61. + heartbeat-led {
  62. + label = "Heartbeat";
  63. + gpios = <&gpio2 31 0>;
  64. + linux,default-trigger = "heartbeat";
  65. + };
  66. + };
  67. +
  68. + soc {
  69. +
  70. +
  71. + hdmi_core: hdmi_core@00120000 {
  72. + compatible = "fsl,imx6q-hdmi-core";
  73. + reg = <0x00120000 0x9000>;
  74. + clocks = <&clks 124>, <&clks 123>;
  75. + clock-names = "hdmi_isfr", "hdmi_iahb";
  76. + status = "disabled";
  77. + };
  78. +
  79. + hdmi_video: hdmi_video@020e0000 {
  80. + compatible = "fsl,imx6q-hdmi-video";
  81. + reg = <0x020e0000 0x1000>;
  82. + reg-names = "hdmi_gpr";
  83. + interrupts = <0 115 0x04>;
  84. + clocks = <&clks 124>, <&clks 123>;
  85. + clock-names = "hdmi_isfr", "hdmi_iahb";
  86. + status = "disabled";
  87. + };
  88. +
  89. + hdmi_audio: hdmi_audio@00120000 {
  90. + compatible = "fsl,imx6q-hdmi-audio";
  91. + clocks = <&clks 124>, <&clks 123>;
  92. + clock-names = "hdmi_isfr", "hdmi_iahb";
  93. + dmas = <&sdma 2 22 0>;
  94. + dma-names = "tx";
  95. + status = "disabled";
  96. + };
  97. +
  98. + };
  99. +
  100. + regulators {
  101. + compatible = "simple-bus";
  102. + #address-cells = <1>;
  103. + #size-cells = <0>;
  104. +
  105. + /* regulator for mmc */
  106. + reg_3p3v: 3p3v {
  107. + compatible = "regulator-fixed";
  108. + regulator-name = "3P3V";
  109. + regulator-min-microvolt = <3300000>;
  110. + regulator-max-microvolt = <3300000>;
  111. + regulator-always-on;
  112. + };
  113. +
  114. + /* regulator for usb otg */
  115. + reg_usb_otg_vbus: usb_otg_vbus {
  116. + compatible = "regulator-fixed";
  117. + regulator-name = "usb_otg_vbus";
  118. + regulator-min-microvolt = <5000000>;
  119. + regulator-max-microvolt = <5000000>;
  120. + gpio = <&gpio3 22 0>;
  121. + enable-active-high;
  122. + };
  123. +
  124. + /* regulator for usb hub1 */
  125. + reg_usb_h1_vbus: usb_h1_vbus {
  126. + compatible = "regulator-fixed";
  127. + regulator-name = "usb_h1_vbus";
  128. + regulator-min-microvolt = <5000000>;
  129. + regulator-max-microvolt = <5000000>;
  130. + gpio = <&gpio7 8 0>;
  131. + enable-active-high;
  132. + };
  133. +
  134. + /* regulator1 for wifi/bt */
  135. + awnh387_npoweron: regulator-awnh387-npoweron {
  136. + compatible = "regulator-fixed";
  137. + regulator-name = "regulator-awnh387-npoweron";
  138. + regulator-min-microvolt = <3300000>;
  139. + regulator-max-microvolt = <3300000>;
  140. + gpio = <&gpio7 12 0>;
  141. + enable-active-high;
  142. + };
  143. +
  144. + /* regulator2 for wifi/bt */
  145. + awnh387_wifi_nreset: regulator-awnh387-wifi-nreset {
  146. + compatible = "regulator-fixed";
  147. + regulator-name = "regulator-awnh387-wifi-nreset";
  148. + regulator-min-microvolt = <3300000>;
  149. + regulator-max-microvolt = <3300000>;
  150. + gpio = <&gpio6 16 0>;
  151. + startup-delay-us = <10000>;
  152. + };
  153. +
  154. + reg_sata_phy_slp: sata_phy_slp {
  155. + compatible = "regulator-fixed";
  156. + regulator-name = "cm_fx6_sata_phy_slp";
  157. + regulator-min-microvolt = <3300000>;
  158. + regulator-max-microvolt = <3300000>;
  159. + gpio = <&gpio3 23 0>;
  160. + startup-delay-us = <100>;
  161. + enable-active-high;
  162. + };
  163. +
  164. + reg_sata_nrstdly: sata_nrstdly {
  165. + compatible = "regulator-fixed";
  166. + regulator-name = "cm_fx6_sata_nrstdly";
  167. + regulator-min-microvolt = <3300000>;
  168. + regulator-max-microvolt = <3300000>;
  169. + gpio = <&gpio6 6 0>;
  170. + startup-delay-us = <100>;
  171. + enable-active-high;
  172. + vin-supply = <&reg_sata_phy_slp>;
  173. + };
  174. +
  175. + reg_sata_pwren: sata_pwren {
  176. + compatible = "regulator-fixed";
  177. + regulator-name = "cm_fx6_sata_pwren";
  178. + regulator-min-microvolt = <3300000>;
  179. + regulator-max-microvolt = <3300000>;
  180. + gpio = <&gpio1 28 0>;
  181. + startup-delay-us = <100>;
  182. + enable-active-high;
  183. + vin-supply = <&reg_sata_nrstdly>;
  184. + };
  185. +
  186. + reg_sata_nstandby1: sata_nstandby1 {
  187. + compatible = "regulator-fixed";
  188. + regulator-name = "cm_fx6_sata_nstandby1";
  189. + regulator-min-microvolt = <3300000>;
  190. + regulator-max-microvolt = <3300000>;
  191. + gpio = <&gpio3 20 0>;
  192. + startup-delay-us = <100>;
  193. + enable-active-high;
  194. + vin-supply = <&reg_sata_pwren>;
  195. + };
  196. +
  197. + reg_sata_nstandby2: sata_nstandby2 {
  198. + compatible = "regulator-fixed";
  199. + regulator-name = "cm_fx6_sata_nstandby2";
  200. + regulator-min-microvolt = <3300000>;
  201. + regulator-max-microvolt = <3300000>;
  202. + gpio = <&gpio5 2 0>;
  203. + startup-delay-us = <100>;
  204. + enable-active-high;
  205. + vin-supply = <&reg_sata_nstandby1>;
  206. + };
  207. +
  208. + reg_sata_ldo_en: sata_ldo_en {
  209. + compatible = "regulator-fixed";
  210. + regulator-name = "cm_fx6_sata_ldo_en";
  211. + regulator-min-microvolt = <3300000>;
  212. + regulator-max-microvolt = <3300000>;
  213. + gpio = <&gpio2 16 0>;
  214. + startup-delay-us = <100>;
  215. + enable-active-high;
  216. + regulator-boot-on;
  217. + vin-supply = <&reg_sata_nstandby2>;
  218. + };
  219. + };
  220. + wm8731_mclk: oscillator {
  221. + compatible = "fixed-clock";
  222. + #clock-cells = <0>;
  223. + clock-frequency = <12000000>;
  224. + clock-output-names = "wm8731-mclk";
  225. + };
  226. +
  227. + gpio-keys {
  228. + compatible = "gpio-keys";
  229. + power {
  230. + label = "Power Button";
  231. + gpios = <&gpio1 29 1>;
  232. + linux,code = <116>; /* KEY_POWER */
  233. + gpio-key,wakeup;
  234. + };
  235. + };
  236. +
  237. + aliases {
  238. + mxcfb0 = &mxcfb1;
  239. + mxcfb1 = &mxcfb2;
  240. + };
  241. + sound {
  242. + compatible = "fsl,imx6q-cm-fx6-wm8731",
  243. + "fsl,imx-audio-wm8731";
  244. + model = "wm8731-audio";
  245. + ssi-controller = <&ssi2>;
  246. + src-port = <2>;
  247. + ext-port = <4>;
  248. + audio-codec = <&codec>;
  249. + audio-routing = "LOUT", "ROUT", "LLINEIN", "RLINEIN";
  250. };
  251. +
  252. + sound-hdmi {
  253. + compatible = "fsl,imx6q-audio-hdmi",
  254. + "fsl,imx-audio-hdmi";
  255. + model = "imx-audio-hdmi";
  256. + hdmi-controller = <&hdmi_audio>;
  257. + };
  258. +
  259. + sound-spdif {
  260. + compatible = "fsl,imx-audio-spdif",
  261. + "fsl,imx-sabreauto-spdif";
  262. + model = "imx-spdif";
  263. + spdif-controller = <&spdif>;
  264. + spdif-out;
  265. + spdif-in;
  266. + };
  267. +
  268. + mxcfb1: fb@0 {
  269. + compatible = "fsl,mxc_sdc_fb";
  270. + disp_dev = "hdmi";
  271. + interface_pix_fmt = "RGB24";
  272. + mode_str ="1920x1080M@60";
  273. + default_bpp = <32>;
  274. + int_clk = <0>;
  275. + late_init = <0>;
  276. + status = "disabled";
  277. + };
  278. +
  279. + mxcfb2: fb@1 {
  280. + compatible = "fsl,mxc_sdc_fb";
  281. + disp_dev = "lcd";
  282. + interface_pix_fmt = "RGB24";
  283. + mode_str ="1920x1080M@60";
  284. + default_bpp = <32>;
  285. + int_clk = <0>;
  286. + late_init = <0>;
  287. + status = "disabled";
  288. + };
  289. +
  290. +
  291. + lcd@0 {
  292. + compatible = "fsl,lcd";
  293. + ipu_id = <0>;
  294. + disp_id = <0>;
  295. + default_ifmt = "RGB24";
  296. + pinctrl-names = "default";
  297. + pinctrl-0 = <&pinctrl_ipu1_1>;
  298. + status = "okay";
  299. + };
  300. +
  301. + v4l2_out {
  302. + compatible = "fsl,mxc_v4l2_output";
  303. + status = "okay";
  304. + };
  305. +
  306. + eth@pcie {
  307. + compatible = "intel,i211";
  308. + local-mac-address = [00 1C 1D 1E 1F 20];
  309. + status = "okay";
  310. + };
  311. +
  312. +};
  313. +
  314. +&iomuxc {
  315. + pinctrl-names = "default";
  316. + pinctrl-0 = <&pinctrl_hog>;
  317. +
  318. + hdmi_hdcp {
  319. + pinctrl_hdmi_hdcp_1: hdmihdcpgrp-1 {
  320. + fsl,pins = <
  321. + MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1
  322. + MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1
  323. + >;
  324. + };
  325. +
  326. + pinctrl_hdmi_hdcp_2: hdmihdcpgrp-2 {
  327. + fsl,pins = <
  328. + MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1
  329. + MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x4001b8b1
  330. + >;
  331. + };
  332. +
  333. + pinctrl_hdmi_hdcp_3: hdmihdcpgrp-3 {
  334. + fsl,pins = <
  335. + MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1
  336. + MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1
  337. + >;
  338. + };
  339. + };
  340. +
  341. +
  342. + ipu2 {
  343. + pinctrl_ipu2_1: ipu2grp-1 {
  344. + fsl,pins = <
  345. + MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0x10
  346. + MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15 0x10
  347. + MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02 0x10
  348. + MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03 0x10
  349. + MX6QDL_PAD_DI0_PIN4__IPU2_DI0_PIN04 0x80000000
  350. + MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00 0x10
  351. + MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01 0x10
  352. + MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02 0x10
  353. + MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03 0x10
  354. + MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04 0x10
  355. + MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05 0x10
  356. + MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06 0x10
  357. + MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07 0x10
  358. + MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08 0x10
  359. + MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09 0x10
  360. + MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10 0x10
  361. + MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11 0x10
  362. + MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12 0x10
  363. + MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13 0x10
  364. + MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14 0x10
  365. + MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15 0x10
  366. + MX6QDL_PAD_DISP0_DAT16__IPU2_DISP0_DATA16 0x10
  367. + MX6QDL_PAD_DISP0_DAT17__IPU2_DISP0_DATA17 0x10
  368. + MX6QDL_PAD_DISP0_DAT18__IPU2_DISP0_DATA18 0x10
  369. + MX6QDL_PAD_DISP0_DAT19__IPU2_DISP0_DATA19 0x10
  370. + MX6QDL_PAD_DISP0_DAT20__IPU2_DISP0_DATA20 0x10
  371. + MX6QDL_PAD_DISP0_DAT21__IPU2_DISP0_DATA21 0x10
  372. + MX6QDL_PAD_DISP0_DAT22__IPU2_DISP0_DATA22 0x10
  373. + MX6QDL_PAD_DISP0_DAT23__IPU2_DISP0_DATA23 0x10
  374. + >;
  375. + };
  376. + };
  377. +
  378. + ipu1 {
  379. + pinctrl_ipu1_1: ipu1grp-1 {
  380. + fsl,pins = <
  381. + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
  382. + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
  383. + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
  384. + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
  385. + MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x80000000
  386. + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
  387. + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
  388. + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
  389. + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
  390. + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
  391. + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
  392. + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
  393. + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
  394. + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
  395. + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
  396. + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
  397. + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
  398. + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
  399. + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
  400. + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
  401. + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
  402. + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
  403. + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
  404. + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
  405. + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
  406. + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
  407. + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
  408. + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
  409. + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
  410. + >;
  411. + };
  412. +
  413. + pinctrl_ipu1_2: ipu1grp-2 { /* parallel camera */
  414. + fsl,pins = <
  415. + MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000
  416. + MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000
  417. + MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000
  418. + MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000
  419. + MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000
  420. + MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000
  421. + MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000
  422. + MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000
  423. + MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x80000000
  424. + MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000
  425. + MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000
  426. + MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000
  427. + >;
  428. + };
  429. +
  430. + pinctrl_ipu1_3: ipu1grp-3 { /* parallel port 16-bit */
  431. + fsl,pins = <
  432. + MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x80000000
  433. + MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x80000000
  434. + MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x80000000
  435. + MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x80000000
  436. + MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x80000000
  437. + MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x80000000
  438. + MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x80000000
  439. + MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x80000000
  440. + MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000
  441. + MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000
  442. + MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000
  443. + MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000
  444. + MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000
  445. + MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000
  446. + MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000
  447. + MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000
  448. + MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000
  449. + MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000
  450. + MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000
  451. + >;
  452. + };
  453. + };
  454. +
  455. + hog {
  456. + pinctrl_hog: hoggrp {
  457. + fsl,pins = <
  458. + /* SATA PWR */
  459. + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x80000000
  460. + MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x80000000
  461. + MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x80000000
  462. + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x80000000
  463. + /* SATA CTRL */
  464. + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000
  465. + MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x80000000
  466. + MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x80000000
  467. + MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000
  468. + >;
  469. + };
  470. + };
  471. +
  472. + imx6q-cm-fx6 {
  473. + /* pins for eth0 */
  474. + pinctrl_enet: enetgrp {
  475. + fsl,pins = <
  476. + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
  477. + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
  478. + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
  479. + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
  480. + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
  481. + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
  482. + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
  483. + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
  484. + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
  485. + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
  486. + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
  487. + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
  488. + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
  489. + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
  490. + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
  491. + >;
  492. + };
  493. +
  494. + /* pins for spi */
  495. + pinctrl_ecspi1: ecspi1grp {
  496. + fsl,pins = <
  497. + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
  498. + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
  499. + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
  500. + MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x100b1
  501. + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x100b1
  502. + >;
  503. + };
  504. +
  505. + /* pins for nand */
  506. + pinctrl_gpmi_nand: gpminandgrp {
  507. + fsl,pins = <
  508. + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
  509. + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
  510. + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
  511. + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
  512. + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
  513. + MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
  514. + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
  515. + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
  516. + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
  517. + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
  518. + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
  519. + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
  520. + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
  521. + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
  522. + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
  523. + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
  524. + MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
  525. + >;
  526. + };
  527. +
  528. + /* pins for i2c1 */
  529. + pinctrl_i2c1: i2c1grp {
  530. + fsl,pins = <
  531. + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
  532. + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
  533. + >;
  534. + };
  535. +
  536. + /* pins for i2c2 */
  537. + pinctrl_i2c2: i2c2grp {
  538. + fsl,pins = <
  539. + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
  540. + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
  541. + >;
  542. + };
  543. +
  544. + /* pins for i2c3 */
  545. + pinctrl_i2c3: i2c3grp {
  546. + fsl,pins = <
  547. + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
  548. + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
  549. + >;
  550. + };
  551. +
  552. + /* pins for console */
  553. + pinctrl_uart4: uart4grp {
  554. + fsl,pins = <
  555. + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
  556. + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
  557. + >;
  558. + };
  559. +
  560. + /* pins for usb hub1 */
  561. + pinctrl_usbh1: usbh1grp {
  562. + fsl,pins = <
  563. + MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x80000000
  564. + >;
  565. + };
  566. +
  567. + /* pins for usb otg */
  568. + pinctrl_usbotg: usbotggrp {
  569. + fsl,pins = <
  570. + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
  571. + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000
  572. + >;
  573. + };
  574. +
  575. + /* pins for wifi/bt */
  576. + pinctrl_usdhc1: usdhc1grp {
  577. + fsl,pins = <
  578. + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071
  579. + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071
  580. + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071
  581. + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071
  582. + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071
  583. + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071
  584. + >;
  585. + };
  586. +
  587. + /* pins for mmc */
  588. + pinctrl_usdhc3: usdhc3grp {
  589. + fsl,pins = <
  590. + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
  591. + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
  592. + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
  593. + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
  594. + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
  595. + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
  596. + >;
  597. + };
  598. +
  599. + /* pins for spdif */
  600. + pinctrl_spdif: spdifgrp {
  601. + fsl,pins = <
  602. + MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0
  603. + MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x1b0b0
  604. + >;
  605. + };
  606. +
  607. + /* pins for audmux */
  608. + pinctrl_audmux: audmuxgrp {
  609. + fsl,pins = <
  610. + MX6QDL_PAD_SD2_CMD__AUD4_RXC 0x17059
  611. + MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x17059
  612. + MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x17059
  613. + MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x17059
  614. + MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x17059
  615. + MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x17059
  616. + >;
  617. + };
  618. +
  619. + /* pins for uart2 */
  620. + pinctrl_uart2: uart2grp {
  621. + fsl,pins = <
  622. + MX6QDL_PAD_GPIO_7__UART2_TX_DATA 0x1b0b1
  623. + MX6QDL_PAD_GPIO_8__UART2_RX_DATA 0x1b0b1
  624. + MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1
  625. + MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1
  626. + >;
  627. + };
  628. +
  629. + /* pins for pcie */
  630. + pinctrl_pcie: pciegrp {
  631. + fsl,pins = <
  632. + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x80000000
  633. + MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x80000000
  634. + >;
  635. + };
  636. + };
  637. };
  638. -
  639. +
  640. +/* spi */
  641. +&ecspi1 {
  642. + fsl,spi-num-chipselects = <2>;
  643. + cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>;
  644. + pinctrl-names = "default";
  645. + pinctrl-0 = <&pinctrl_ecspi1>;
  646. + status = "okay";
  647. +
  648. + flash: m25p80@0 {
  649. + #address-cells = <1>;
  650. + #size-cells = <1>;
  651. + compatible = "st,m25px16", "st,m25p";
  652. + spi-max-frequency = <20000000>;
  653. + reg = <0>;
  654. +
  655. + partition@0 {
  656. + label = "uboot";
  657. + reg = <0x0 0xc0000>;
  658. + };
  659. +
  660. + partition@c0000 {
  661. + label = "uboot environment";
  662. + reg = <0xc0000 0x40000>;
  663. + };
  664. +
  665. + partition@100000 {
  666. + label = "reserved";
  667. + reg = <0x100000 0x100000>;
  668. + };
  669. + };
  670. +};
  671. +
  672. +/* eth0 */
  673. &fec {
  674. - pinctrl-names = "default";
  675. - pinctrl-0 = <&pinctrl_enet>;
  676. - phy-mode = "rgmii";
  677. - status = "okay";
  678. + pinctrl-names = "default";
  679. + pinctrl-0 = <&pinctrl_enet>;
  680. + phy-mode = "rgmii";
  681. + status = "okay";
  682. };
  683. -
  684. +
  685. +/* nand */
  686. &gpmi {
  687. - pinctrl-names = "default";
  688. - pinctrl-0 = <&pinctrl_gpmi_nand>;
  689. - status = "okay";
  690. + pinctrl-names = "default";
  691. + pinctrl-0 = <&pinctrl_gpmi_nand>;
  692. + status = "okay";
  693. };
  694. -
  695. -&iomuxc {
  696. - imx6q-cm-fx6 {
  697. - pinctrl_enet: enetgrp {
  698. - fsl,pins = <
  699. - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
  700. - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
  701. - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
  702. - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
  703. - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
  704. - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
  705. - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
  706. - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
  707. - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
  708. - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
  709. - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
  710. - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
  711. - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
  712. - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
  713. - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
  714. - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
  715. - >;
  716. - };
  717. -
  718. - pinctrl_gpmi_nand: gpminandgrp {
  719. - fsl,pins = <
  720. - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
  721. - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
  722. - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
  723. - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
  724. - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
  725. - MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
  726. - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
  727. - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
  728. - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
  729. - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
  730. - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
  731. - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
  732. - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
  733. - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
  734. - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
  735. - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
  736. - MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
  737. - >;
  738. - };
  739. -
  740. - pinctrl_uart4: uart4grp {
  741. - fsl,pins = <
  742. - MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
  743. - MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
  744. - >;
  745. - };
  746. - };
  747. +
  748. +/* i2c1 */
  749. +&i2c1 {
  750. + pinctrl-names = "default";
  751. + pinctrl-0 = <&pinctrl_i2c1>;
  752. + status = "okay";
  753. +
  754. + eeprom@50 {
  755. + compatible = "at24,24c02";
  756. + reg = <0x50>;
  757. + pagesize = <16>;
  758. + };
  759. +
  760. + rtc@56 {
  761. + compatible = "emmicro,em3027";
  762. + reg = <0x56>;
  763. + };
  764. };
  765. -
  766. +
  767. +/* i2c2 */
  768. +&i2c2 {
  769. + pinctrl-names = "default";
  770. + pinctrl-0 = <&pinctrl_i2c2>;
  771. + /* status = "okay"; */
  772. +};
  773. +
  774. +/* i2c3 */
  775. +&i2c3 {
  776. + pinctrl-names = "default";
  777. + pinctrl-0 = <&pinctrl_i2c3>;
  778. + status = "okay";
  779. + clock-frequency = <100000>;
  780. + eeprom@50 {
  781. + compatible = "at24,24c02";
  782. + reg = <0x50>;
  783. + pagesize = <16>;
  784. + };
  785. +
  786. + codec: wm8731@1a {
  787. + compatible = "wlf,wm8731";
  788. + reg = <0x1a>;
  789. + clocks = <&clks 173>, <&clks 158>, <&clks 201>, <&clks 200>;
  790. + clock-names = "pll4", "imx-ssi.1", "cko", "cko2";
  791. + AVDD-supply = <&reg_3p3v>;
  792. + HPVDD-supply = <&reg_3p3v>;
  793. + DCVDD-supply = <&reg_3p3v>;
  794. + DBVDD-supply = <&reg_3p3v>;
  795. + };
  796. +};
  797. +
  798. +/* eth1 */
  799. +&pcie {
  800. + pinctrl-names = "default";
  801. + pinctrl-0 = <&pinctrl_pcie>;
  802. + reset-gpio = <&gpio1 26 0>;
  803. + power-on-gpio = <&gpio2 24 0>;
  804. + status = "okay";
  805. +};
  806. +
  807. +/* sata */
  808. +&sata {
  809. + status = "okay";
  810. +};
  811. +
  812. +/* rear serial console */
  813. +&uart2 {
  814. + pinctrl-names = "default";
  815. + pinctrl-0 = <&pinctrl_uart2>;
  816. + /* fsl,dte-mode; */
  817. + fsl,uart-has-rtscts;
  818. + dma-names = "rx", "tx";
  819. + dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
  820. + status = "okay";
  821. +};
  822. +
  823. +/* console */
  824. &uart4 {
  825. - pinctrl-names = "default";
  826. - pinctrl-0 = <&pinctrl_uart4>;
  827. - status = "okay";
  828. + pinctrl-names = "default";
  829. + pinctrl-0 = <&pinctrl_uart4>;
  830. + status = "okay";
  831. +};
  832. +
  833. +/* usb otg */
  834. +&usbotg {
  835. + vbus-supply = <&reg_usb_otg_vbus>;
  836. + pinctrl-names = "default";
  837. + pinctrl-0 = <&pinctrl_usbotg>;
  838. + dr_mode = "otg";
  839. + status = "okay";
  840. +};
  841. +
  842. +/* usb hub1 */
  843. +&usbh1 {
  844. + vbus-supply = <&reg_usb_h1_vbus>;
  845. + pinctrl-names = "default";
  846. + pinctrl-0 = <&pinctrl_usbh1>;
  847. + status = "okay";
  848. +};
  849. +
  850. +/* wifi/bt */
  851. +&usdhc1 {
  852. + pinctrl-names = "default";
  853. + pinctrl-0 = <&pinctrl_usdhc1>;
  854. + non-removable;
  855. + vmmc-supply = <&awnh387_npoweron>;
  856. + vmmc_aux-supply = <&awnh387_wifi_nreset>;
  857. + status = "okay";
  858. +};
  859. +
  860. +/* mmc */
  861. +&usdhc3 {
  862. + pinctrl-names = "default";
  863. + pinctrl-0 = <&pinctrl_usdhc3>;
  864. + vmmc-supply = <&reg_3p3v>;
  865. + status = "okay";
  866. +};
  867. +
  868. +&ssi2 {
  869. + fsl,mode = "i2s-master";
  870. + status = "okay";
  871. +};
  872. +
  873. +&mxcfb1 {
  874. + status = "okay";
  875. +};
  876. +
  877. +&mxcfb2 {
  878. + status = "okay";
  879. +};
  880. +
  881. +&hdmi_core {
  882. + ipu_id = <1>;
  883. + disp_id = <0>;
  884. + status = "okay";
  885. +};
  886. +
  887. +&hdmi_video {
  888. + pinctrl-names = "default";
  889. + pinctrl-0 = <&pinctrl_hdmi_hdcp_1>;
  890. + fsl,hdcp;
  891. + status = "okay";
  892. +};
  893. +
  894. +&hdmi_audio {
  895. + status = "okay";
  896. +};
  897. +
  898. +&spdif {
  899. + pinctrl-names = "default";
  900. + pinctrl-0 = <&pinctrl_spdif>;
  901. + status = "okay";
  902. +};
  903. +
  904. +&audmux {
  905. + pinctrl-names = "default";
  906. + pinctrl-0 = <&pinctrl_audmux>;
  907. + status = "okay";
  908. };
  909. diff --git a/drivers/net/ethernet/intel/igb/igb_main.c b/drivers/net/ethernet/intel/igb/igb_main.c
  910. index a21b144..9d2b14b 100644
  911. --- a/drivers/net/ethernet/intel/igb/igb_main.c
  912. +++ b/drivers/net/ethernet/intel/igb/igb_main.c
  913. @@ -2222,6 +2222,32 @@ static s32 igb_init_i2c(struct igb_adapter *adapter)
  914. return status;
  915. }
  916.  
  917. +
  918. +/**
  919. + * igb_read_mac_addr_dts - Read mac address from the device tree
  920. + * blob
  921. + * @adapter: pointer to adapter structure
  922. + **/
  923. +static void igb_read_mac_addr_dts(struct e1000_hw *hw)
  924. +{
  925. + struct device_node *dn;
  926. + const uint8_t *mac;
  927. +
  928. + dn = of_find_compatible_node(NULL, NULL, "intel,i211");
  929. +
  930. + if (!dn)
  931. + return;
  932. +
  933. + mac = of_get_property(dn, "local-mac-address", NULL);
  934. +
  935. + if (mac)
  936. + memcpy(hw->mac.addr, mac, ETH_ALEN);
  937. +
  938. + return;
  939. +}
  940. +
  941. +
  942. +
  943. /**
  944. * igb_probe - Device Initialization Routine
  945. * @pdev: PCI device information struct
  946. @@ -2424,6 +2450,15 @@ static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  947. if (hw->mac.ops.read_mac_addr(hw))
  948. dev_err(&pdev->dev, "NVM Read Error\n");
  949.  
  950. +
  951. + if (!is_valid_ether_addr(hw->mac.addr))
  952. + igb_read_mac_addr_dts(hw);
  953. +
  954. + if (!is_valid_ether_addr(hw->mac.addr)) {
  955. + dev_info(&pdev->dev, "Random MAC Address\n");
  956. + random_ether_addr(hw->mac.addr);
  957. + }
  958. +
  959. memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
  960.  
  961. if (!is_valid_ether_addr(netdev->dev_addr)) {
  962. diff --git a/sound/soc/fsl/Kconfig b/sound/soc/fsl/Kconfig
  963. index 081e406..09c923f 100644
  964. --- a/sound/soc/fsl/Kconfig
  965. +++ b/sound/soc/fsl/Kconfig
  966. @@ -229,6 +229,17 @@ config SND_SOC_EUKREA_TLV320
  967. Enable I2S based access to the TLV320AIC23B codec attached
  968. to the SSI interface
  969.  
  970. +config SND_SOC_IMX_WM8731
  971. + tristate "SoC Audio support for i.MX boards with wm8731
  972. + depends on OF && I2C
  973. + select SND_SOC_WM8731
  974. + select SND_SOC_IMX_PCM_DMA
  975. + select SND_SOC_IMX_AUDMUX
  976. + select SND_SOC_FSL_SSI
  977. + select SND_SOC_FSL_UTILS
  978. + help
  979. + Soc Audio support for i.MX with wm8731
  980. +
  981. config SND_SOC_IMX_WM8962
  982. tristate "SoC Audio support for i.MX boards with wm8962"
  983. depends on OF && I2C && INPUT
  984. diff --git a/sound/soc/fsl/Makefile b/sound/soc/fsl/Makefile
  985. index d28dc25..4292fac 100644
  986. --- a/sound/soc/fsl/Makefile
  987. +++ b/sound/soc/fsl/Makefile
  988. @@ -54,6 +54,7 @@ snd-soc-mx27vis-aic32x4-objs := mx27vis-aic32x4.o
  989. snd-soc-wm1133-ev1-objs := wm1133-ev1.o
  990. snd-soc-imx-es8328-objs := imx-es8328.o
  991. snd-soc-imx-sgtl5000-objs := imx-sgtl5000.o
  992. +snd-soc-imx-wm8731-objs := imx-wm8731.o
  993. snd-soc-imx-wm8962-objs := imx-wm8962.o
  994. snd-soc-imx-spdif-objs := imx-spdif.o
  995. snd-soc-imx-mc13783-objs := imx-mc13783.o
  996. @@ -65,5 +66,6 @@ obj-$(CONFIG_SND_MXC_SOC_WM1133_EV1) += snd-soc-wm1133-ev1.o
  997. obj-$(CONFIG_SND_SOC_IMX_ES8328) += snd-soc-imx-es8328.o
  998. obj-$(CONFIG_SND_SOC_IMX_SGTL5000) += snd-soc-imx-sgtl5000.o
  999. obj-$(CONFIG_SND_SOC_IMX_WM8962) += snd-soc-imx-wm8962.o
  1000. +obj-$(CONFIG_SND_SOC_IMX_WM8731) += snd-soc-imx-wm8731.o
  1001. obj-$(CONFIG_SND_SOC_IMX_SPDIF) += snd-soc-imx-spdif.o
  1002. obj-$(CONFIG_SND_SOC_IMX_MC13783) += snd-soc-imx-mc13783.o
  1003. diff --git a/sound/soc/fsl/imx-wm8731.c b/sound/soc/fsl/imx-wm8731.c
  1004. new file mode 100644
  1005. index 0000000..277a785
  1006. --- /dev/null
  1007. +++ b/sound/soc/fsl/imx-wm8731.c
  1008. @@ -0,0 +1,687 @@
  1009. +/*
  1010. + * Copyright (C) 2014 Freescale Semiconductor, Inc.
  1011. + *
  1012. + * Based on imx-sgtl5000.c
  1013. + * Copyright (C) 2012 Freescale Semiconductor, Inc.
  1014. + * Copyright (C) 2012 Linaro Ltd.
  1015. + *
  1016. + * The code contained herein is licensed under the GNU General Public
  1017. + * License. You may obtain a copy of the GNU General Public License
  1018. + * Version 2 or later at the following locations:
  1019. + *
  1020. + * http://www.opensource.org/licenses/gpl-license.html
  1021. + * http://www.gnu.org/copyleft/gpl.html
  1022. + */
  1023. +
  1024. +#include <linux/module.h>
  1025. +#include <linux/of_platform.h>
  1026. +#include <linux/i2c.h>
  1027. +#include <linux/of_gpio.h>
  1028. +#include <linux/slab.h>
  1029. +#include <linux/gpio.h>
  1030. +#include <linux/clk.h>
  1031. +#include <sound/soc.h>
  1032. +#include <sound/jack.h>
  1033. +#include <sound/pcm_params.h>
  1034. +#include <sound/soc-dapm.h>
  1035. +#include <linux/pinctrl/consumer.h>
  1036. +
  1037. +#include "../codecs/wm8731.h"
  1038. +#include "imx-audmux.h"
  1039. +#include "imx-ssi.h"
  1040. +
  1041. +#define DAI_NAME_SIZE 32
  1042. +#define WM8731_MCLK_FREQ (24000000 / 2)
  1043. +
  1044. +struct imx_wm8731_data {
  1045. + struct snd_soc_dai_link dai;
  1046. + struct snd_soc_card card;
  1047. + char codec_dai_name[DAI_NAME_SIZE];
  1048. + char platform_name[DAI_NAME_SIZE];
  1049. + struct i2c_client *codec_dev;
  1050. + /* audio_clocking_data */
  1051. + struct clk *pll;
  1052. + struct clk *clock_root;
  1053. + long sysclk;
  1054. + long current_rate;
  1055. + /* apis */
  1056. + int (*clock_enable)(int enable,struct imx_wm8731_data *data);
  1057. +};
  1058. +
  1059. +static int imx_wm8731_init(struct snd_soc_pcm_runtime *rtd);
  1060. +static int imx_hifi_hw_params_slv_mode(struct snd_pcm_substream *substream,
  1061. + struct snd_pcm_hw_params *params);
  1062. +static void imx_hifi_shutdown(struct snd_pcm_substream *substream);
  1063. +
  1064. +struct imx_priv {
  1065. + struct platform_device *pdev;
  1066. + struct imx_wm8731_data *data;
  1067. +};
  1068. +
  1069. +static struct imx_priv card_priv;
  1070. +
  1071. +static struct snd_soc_ops imx_hifi_ops = {
  1072. + .shutdown = imx_hifi_shutdown,
  1073. +};
  1074. +
  1075. +/* imx card dapm widgets */
  1076. +static const struct snd_soc_dapm_widget imx_dapm_widgets[] = {
  1077. + SND_SOC_DAPM_HP("Headphone Jack", NULL),
  1078. + SND_SOC_DAPM_SPK("Ext Spk", NULL),
  1079. + SND_SOC_DAPM_LINE("Line Jack", NULL),
  1080. + SND_SOC_DAPM_MIC("Mic Jack", NULL),
  1081. +};
  1082. +
  1083. +/* imx machine connections to the codec pins */
  1084. +static const struct snd_soc_dapm_route audio_map[] = {
  1085. + { "Headphone Jack", NULL, "LHPOUT" },
  1086. + { "Headphone Jack", NULL, "RHPOUT" },
  1087. +
  1088. + { "Ext Spk", NULL, "LOUT" },
  1089. + { "Ext Spk", NULL, "ROUT" },
  1090. +
  1091. + { "LLINEIN", NULL, "Line Jack" },
  1092. + { "RLINEIN", NULL, "Line Jack" },
  1093. +
  1094. + { "MICIN", NULL, "Mic Bias" },
  1095. + { "Mic Bias", NULL, "Mic Jack"},
  1096. +};
  1097. +
  1098. +static int wm8731_slv_mode_init(struct imx_wm8731_data *data)
  1099. +{
  1100. + struct clk *new_parent;
  1101. + struct clk *ssi_clk;
  1102. + struct i2c_client *codec_dev = data->codec_dev;
  1103. +
  1104. + new_parent = devm_clk_get(&codec_dev->dev, "pll4");
  1105. + if (IS_ERR(new_parent)) {
  1106. + pr_err("Could not get \"pll4\" clock \n");
  1107. + return PTR_ERR(new_parent);
  1108. + }
  1109. +
  1110. + ssi_clk = devm_clk_get(&codec_dev->dev, "imx-ssi.1");
  1111. + if (IS_ERR(ssi_clk)) {
  1112. + pr_err("Could not get \"imx-ssi.1\" clock \n");
  1113. + return PTR_ERR(ssi_clk);
  1114. + }
  1115. +
  1116. + clk_set_parent(ssi_clk, new_parent);
  1117. +
  1118. + data->pll = new_parent;
  1119. + data->clock_root = ssi_clk;
  1120. + data->current_rate = 0;
  1121. +
  1122. + data->sysclk = 0;
  1123. +
  1124. + return 0;
  1125. +}
  1126. +
  1127. +static int wm8731_slv_mode_clock_enable(int enable, struct imx_wm8731_data *data)
  1128. +{
  1129. + long pll_rate;
  1130. + long rate_req;
  1131. + long rate_avail;
  1132. +
  1133. + if (!enable)
  1134. + return 0;
  1135. +
  1136. + if (data->sysclk == data->current_rate)
  1137. + return 0;
  1138. +
  1139. + switch (data->sysclk) {
  1140. + case 11289600:
  1141. + pll_rate = 632217600;
  1142. + break;
  1143. +
  1144. + case 12288000:
  1145. + pll_rate = 688128000;
  1146. + break;
  1147. +
  1148. + default:
  1149. + return -EINVAL;
  1150. + }
  1151. +
  1152. + rate_req = pll_rate;
  1153. + rate_avail = clk_round_rate(data->pll, rate_req);
  1154. + clk_set_rate(data->pll, rate_avail);
  1155. +
  1156. + rate_req = data->sysclk;
  1157. + rate_avail = clk_round_rate(data->clock_root,
  1158. + rate_req);
  1159. + clk_set_rate(data->clock_root, rate_avail);
  1160. +
  1161. + pr_info("%s: \"imx-ssi.1\" rate = %ld (= %ld)\n",
  1162. + __func__, rate_avail, rate_req);
  1163. +
  1164. + data->current_rate = data->sysclk;
  1165. +
  1166. + return 0;
  1167. +}
  1168. +
  1169. +static int imx_hifi_startup_slv_mode(struct snd_pcm_substream *substream)
  1170. +{
  1171. + /*
  1172. + * As SSI's sys clock rate depends on sampling rate,
  1173. + * the clock enabling code is moved to imx_hifi_hw_params().
  1174. + */
  1175. + return 0;
  1176. +}
  1177. +
  1178. +static int wm8731_mst_mode_init(struct imx_wm8731_data *data)
  1179. +{
  1180. + long rate;
  1181. + struct clk *new_parent;
  1182. + struct clk *ssi_clk;
  1183. + struct i2c_client *codec_dev = data->codec_dev;
  1184. +
  1185. + new_parent = devm_clk_get(&codec_dev->dev, "cko2");
  1186. + if (IS_ERR(new_parent)) {
  1187. + pr_err("Could not get \"cko2\" clock \n");
  1188. + return PTR_ERR(new_parent);
  1189. + }
  1190. +
  1191. + ssi_clk = devm_clk_get(&codec_dev->dev, "cko");
  1192. + if (IS_ERR(ssi_clk)) {
  1193. + pr_err("Could not get \"cko\" clock \n");
  1194. + return PTR_ERR(ssi_clk);
  1195. + }
  1196. +
  1197. + rate = clk_round_rate(new_parent, WM8731_MCLK_FREQ);
  1198. + clk_set_rate(new_parent, rate);
  1199. +
  1200. + clk_set_parent(ssi_clk, new_parent);
  1201. +
  1202. + rate = clk_round_rate(ssi_clk, WM8731_MCLK_FREQ);
  1203. + clk_set_rate(ssi_clk, rate);
  1204. +
  1205. + pr_info("%s: \"CLKO\" rate = %ld (= %d)\n",
  1206. + __func__, rate, WM8731_MCLK_FREQ);
  1207. +
  1208. + data->pll = new_parent;
  1209. + data->clock_root = ssi_clk;
  1210. + data->sysclk = rate;
  1211. +
  1212. + return 0;
  1213. +}
  1214. +
  1215. +static int wm8731_mst_mode_clock_enable(int enable, struct imx_wm8731_data *data)
  1216. +{
  1217. + struct clk *clko = data->clock_root;
  1218. +
  1219. + if (enable)
  1220. + clk_enable(clko);
  1221. + else
  1222. + clk_disable(clko);
  1223. +
  1224. + return 0;
  1225. +}
  1226. +
  1227. +static int imx_hifi_startup_mst_mode(struct snd_pcm_substream *substream)
  1228. +{
  1229. + struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1230. + struct snd_soc_dai *codec_dai = rtd->codec_dai;
  1231. + struct snd_soc_card *card = codec_dai->card;
  1232. + struct imx_wm8731_data *data = snd_soc_card_get_drvdata(card);
  1233. +
  1234. + if (!codec_dai->active)
  1235. + data->clock_enable(1,data);
  1236. +
  1237. + return 0;
  1238. +}
  1239. +
  1240. +
  1241. +static int imx_hifi_hw_params_slv_mode(struct snd_pcm_substream *substream,
  1242. + struct snd_pcm_hw_params *params)
  1243. +{
  1244. + struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1245. + struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  1246. + struct snd_soc_dai *codec_dai = rtd->codec_dai;
  1247. + struct snd_soc_card *card = codec_dai->card;
  1248. + struct imx_wm8731_data *data = snd_soc_card_get_drvdata(card);
  1249. +
  1250. + u32 dai_format;
  1251. + snd_pcm_format_t sample_format;
  1252. + unsigned int channels;
  1253. + unsigned int tx_mask, rx_mask;
  1254. + unsigned int sampling_rate;
  1255. + unsigned int div_2, div_psr, div_pm;
  1256. + int ret;
  1257. +
  1258. + sampling_rate = params_rate(params);
  1259. + sample_format = params_format(params);
  1260. +
  1261. + channels = params_channels(params);
  1262. + printk("%s:%s sampling rate = %u channels = %u \n", __FUNCTION__,
  1263. + (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? "Playback" : "Capture"),
  1264. + sampling_rate, channels);
  1265. +
  1266. + /* set CPU DAI configuration */
  1267. + switch (sampling_rate) {
  1268. + case 8000:
  1269. + case 32000:
  1270. + case 48000:
  1271. + case 96000:
  1272. + data->sysclk = 12288000;
  1273. + break;
  1274. +
  1275. + case 44100:
  1276. + case 88200:
  1277. + data->sysclk = 11289600;
  1278. + break;
  1279. +
  1280. + default:
  1281. + return -EINVAL;
  1282. + }
  1283. +
  1284. + wm8731_slv_mode_clock_enable(1,data);
  1285. +
  1286. + dai_format = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_IF |
  1287. + SND_SOC_DAIFMT_CBS_CFS;
  1288. +
  1289. + ret = snd_soc_dai_set_fmt(cpu_dai, dai_format);
  1290. + if (ret < 0)
  1291. + return ret;
  1292. +
  1293. + /* set i.MX active slot mask */
  1294. + /* S[TR]CCR:DC */
  1295. + tx_mask = ~((1 << channels) - 1);
  1296. + rx_mask = tx_mask;
  1297. + snd_soc_dai_set_tdm_slot(cpu_dai, tx_mask, rx_mask, 2, 32);
  1298. +
  1299. + /*
  1300. + * SSI sysclk divider:
  1301. + * div_2: /1 or /2
  1302. + * div_psr: /1 or /8
  1303. + * div_pm: /1 .. /256
  1304. + */
  1305. + div_2 = 0;
  1306. + div_psr = 0;
  1307. + switch (sampling_rate) {
  1308. + case 8000:
  1309. + // 1x1x12
  1310. + div_pm = 11;
  1311. + break;
  1312. + case 32000:
  1313. + // 1x1x3
  1314. + div_pm = 2;
  1315. + break;
  1316. + case 48000:
  1317. + // 1x1x2
  1318. + div_pm = 1;
  1319. + break;
  1320. + case 96000:
  1321. + // 1x1x1
  1322. + div_pm = 0;
  1323. + break;
  1324. + case 44100:
  1325. + // 1x1x2
  1326. + div_pm = 1;
  1327. + break;
  1328. + case 88200:
  1329. + // 1x1x1
  1330. + div_pm = 0;
  1331. + break;
  1332. + default:
  1333. + return -EINVAL;
  1334. + }
  1335. +
  1336. + /* sync mode: a single clock controls both playback and capture */
  1337. + snd_soc_dai_set_clkdiv(cpu_dai, IMX_SSI_TX_DIV_2, (div_2 ? SSI_STCCR_DIV2 : 0));
  1338. + snd_soc_dai_set_clkdiv(cpu_dai, IMX_SSI_TX_DIV_PSR, (div_psr ? SSI_STCCR_PSR : 0));
  1339. + snd_soc_dai_set_clkdiv(cpu_dai, IMX_SSI_TX_DIV_PM, div_pm);
  1340. +
  1341. + /* set codec DAI configuration */
  1342. + dai_format = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
  1343. + SND_SOC_DAIFMT_CBS_CFS;
  1344. +
  1345. + ret = snd_soc_dai_set_fmt(codec_dai, dai_format);
  1346. + if (ret < 0)
  1347. + return ret;
  1348. +
  1349. + ret = snd_soc_dai_set_sysclk(codec_dai,
  1350. + WM8731_SYSCLK_MCLK,
  1351. + data->sysclk,
  1352. + SND_SOC_CLOCK_IN);
  1353. +
  1354. + if (ret < 0) {
  1355. + pr_err("Failed to set codec master clock to %u: %d \n",
  1356. + data->sysclk, ret);
  1357. + return ret;
  1358. + }
  1359. +
  1360. + return 0;
  1361. +}
  1362. +
  1363. +static int imx_hifi_hw_params_mst_mode(struct snd_pcm_substream *substream,
  1364. + struct snd_pcm_hw_params *params)
  1365. +{
  1366. + struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1367. + struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  1368. + struct snd_soc_dai *codec_dai = rtd->codec_dai;
  1369. + struct snd_soc_card *card = codec_dai->card;
  1370. + struct imx_wm8731_data *data = snd_soc_card_get_drvdata(card);
  1371. + u32 dai_format;
  1372. + unsigned int channels;
  1373. + unsigned int tx_mask, rx_mask;
  1374. + unsigned int sampling_rate;
  1375. + int ret;
  1376. +
  1377. +
  1378. + sampling_rate = params_rate(params);
  1379. + channels = params_channels(params);
  1380. + pr_debug("%s:%s sampling rate = %u channels = %u \n", __FUNCTION__,
  1381. + (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? "Playback" : "Capture"),
  1382. + sampling_rate, channels);
  1383. +
  1384. + /* set cpu DAI configuration */
  1385. + dai_format = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_IF |
  1386. + SND_SOC_DAIFMT_CBM_CFM;
  1387. +
  1388. + ret = snd_soc_dai_set_fmt(cpu_dai, dai_format);
  1389. + if (ret < 0)
  1390. + return ret;
  1391. +
  1392. + /* set i.MX active slot mask */
  1393. + /* S[TR]CCR:DC */
  1394. + tx_mask = ~((1 << channels) - 1);
  1395. + rx_mask = tx_mask;
  1396. + snd_soc_dai_set_tdm_slot(cpu_dai, tx_mask, rx_mask, 2, 32);
  1397. +
  1398. + /* set codec DAI configuration */
  1399. + dai_format = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
  1400. + SND_SOC_DAIFMT_CBM_CFM;
  1401. +
  1402. + ret = snd_soc_dai_set_fmt(codec_dai, dai_format);
  1403. + if (ret < 0)
  1404. + return ret;
  1405. +
  1406. + ret = snd_soc_dai_set_sysclk(codec_dai,
  1407. + WM8731_SYSCLK_MCLK,
  1408. + data->sysclk,
  1409. + SND_SOC_CLOCK_IN);
  1410. +
  1411. + if (ret < 0) {
  1412. + pr_err("Failed to set codec master clock to %u: %d \n",
  1413. + data->sysclk, ret);
  1414. + return ret;
  1415. + }
  1416. +
  1417. + return 0;
  1418. +}
  1419. +
  1420. +static void imx_hifi_shutdown(struct snd_pcm_substream *substream)
  1421. +{
  1422. + struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1423. + struct snd_soc_dai *codec_dai = rtd->codec_dai;
  1424. + struct snd_soc_card *card = codec_dai->card;
  1425. + struct imx_wm8731_data *data = snd_soc_card_get_drvdata(card);
  1426. +
  1427. + if (!codec_dai->active)
  1428. + data->clock_enable(0,data);
  1429. +
  1430. + return;
  1431. +}
  1432. +
  1433. +static int imx_wm8731_init(struct snd_soc_pcm_runtime *rtd)
  1434. +{
  1435. + int ret = 0;
  1436. + struct snd_soc_codec *codec = rtd->codec;
  1437. +
  1438. + /* Add imx specific widgets */
  1439. + ret = snd_soc_dapm_new_controls(&codec->dapm, imx_dapm_widgets,
  1440. + ARRAY_SIZE(imx_dapm_widgets));
  1441. + if (ret)
  1442. + goto out_retcode;
  1443. +
  1444. + /* Set up imx specific audio path audio_map */
  1445. + ret = snd_soc_dapm_add_routes(&codec->dapm, audio_map, ARRAY_SIZE(audio_map));
  1446. + if (ret)
  1447. + goto out_retcode;
  1448. +
  1449. + ret = snd_soc_dapm_enable_pin(&codec->dapm, "Headphone Jack");
  1450. + if (ret)
  1451. + goto out_retcode;
  1452. +
  1453. + ret = snd_soc_dapm_nc_pin(&codec->dapm, "Ext Spk");
  1454. + if (ret)
  1455. + goto out_retcode;
  1456. +
  1457. +out_retcode:
  1458. +
  1459. + if (ret)
  1460. + pr_err("%s: failed with error code: %d \n", __FUNCTION__, ret);
  1461. + else
  1462. + pr_info("%s: success \n", __FUNCTION__);
  1463. +
  1464. + return ret;
  1465. +}
  1466. +
  1467. +/**
  1468. + * Configure AUDMUX interconnection between
  1469. + * _slave (CPU side) and _master (codec size)
  1470. + *
  1471. + * When SSI operates in master mode, 5-wire interconnect with
  1472. + * audio codec is required:
  1473. + * TXC - BCLK
  1474. + * TXD - DAC data
  1475. + * RXD - ADC data
  1476. + * TXFS - {DAC|ADC}LRC, i.e. word clock
  1477. + * RXC - MCLK, i.e. oversampling clock
  1478. + * Audmux is operated in asynchronous mode to enable 6-wire
  1479. + * interface (as opposed to 4-wire interface in sync mode).
  1480. + */
  1481. +static int imx_audmux_config_slv_mode(int _slave, int _master)
  1482. +{
  1483. + unsigned int ptcr, pdcr;
  1484. + int slave = _slave - 1;
  1485. + int master = _master - 1;
  1486. +
  1487. + ptcr = IMX_AUDMUX_V2_PTCR_SYN |
  1488. + IMX_AUDMUX_V2_PTCR_TFSDIR |
  1489. + IMX_AUDMUX_V2_PTCR_TFSEL(slave) |
  1490. + IMX_AUDMUX_V2_PTCR_RCLKDIR |
  1491. + IMX_AUDMUX_V2_PTCR_RCSEL(slave | 0x8) |
  1492. + IMX_AUDMUX_V2_PTCR_TCLKDIR |
  1493. + IMX_AUDMUX_V2_PTCR_TCSEL(slave);
  1494. +
  1495. + pdcr = IMX_AUDMUX_V2_PDCR_RXDSEL(slave);
  1496. + imx_audmux_v2_configure_port(master, ptcr, pdcr);
  1497. + ptcr = ptcr & ~IMX_AUDMUX_V2_PTCR_SYN;
  1498. + imx_audmux_v2_configure_port(master, ptcr, pdcr);
  1499. +
  1500. + ptcr = IMX_AUDMUX_V2_PTCR_SYN |
  1501. + IMX_AUDMUX_V2_PTCR_RCLKDIR |
  1502. + IMX_AUDMUX_V2_PTCR_RCSEL(master | 0x8) |
  1503. + IMX_AUDMUX_V2_PTCR_TCLKDIR |
  1504. + IMX_AUDMUX_V2_PTCR_TCSEL(master);
  1505. +
  1506. + pdcr = IMX_AUDMUX_V2_PDCR_RXDSEL(master);
  1507. + imx_audmux_v2_configure_port(slave, ptcr, pdcr);
  1508. + ptcr = ptcr & ~IMX_AUDMUX_V2_PTCR_SYN;
  1509. + imx_audmux_v2_configure_port(slave, ptcr, pdcr);
  1510. +
  1511. + return 0;
  1512. +}
  1513. +
  1514. +static int imx_audmux_config_mst_mode(int _slave, int _master)
  1515. +{
  1516. + unsigned int ptcr, pdcr;
  1517. + int slave = _slave - 1;
  1518. + int master = _master - 1;
  1519. +
  1520. + ptcr = IMX_AUDMUX_V2_PTCR_SYN;
  1521. + ptcr |= IMX_AUDMUX_V2_PTCR_TFSDIR |
  1522. + IMX_AUDMUX_V2_PTCR_TFSEL(master) |
  1523. + IMX_AUDMUX_V2_PTCR_TCLKDIR |
  1524. + IMX_AUDMUX_V2_PTCR_TCSEL(master);
  1525. + pdcr = IMX_AUDMUX_V2_PDCR_RXDSEL(master);
  1526. + imx_audmux_v2_configure_port(slave, ptcr, pdcr);
  1527. +
  1528. + ptcr = IMX_AUDMUX_V2_PTCR_SYN;
  1529. + pdcr = IMX_AUDMUX_V2_PDCR_RXDSEL(slave);
  1530. + imx_audmux_v2_configure_port(master, ptcr, pdcr);
  1531. +
  1532. + return 0;
  1533. +}
  1534. +
  1535. +static int imx_wm8731_probe(struct platform_device *pdev)
  1536. +{
  1537. + struct device_node *ssi_np, *codec_np;
  1538. + struct platform_device *ssi_pdev;
  1539. + struct imx_priv *priv = &card_priv;
  1540. + struct i2c_client *codec_dev;
  1541. + struct imx_wm8731_data *data;
  1542. + unsigned int src_port, ext_port;
  1543. + unsigned int ssi_mode;
  1544. + const char *ssi_mode_str;
  1545. +
  1546. + int ret;
  1547. +
  1548. + priv->pdev = pdev;
  1549. +
  1550. + ssi_np = of_parse_phandle(pdev->dev.of_node, "ssi-controller", 0);
  1551. + codec_np = of_parse_phandle(pdev->dev.of_node, "audio-codec", 0);
  1552. + if (!ssi_np || !codec_np) {
  1553. + dev_err(&pdev->dev, "phandle missing or invalid\n");
  1554. + ret = -EINVAL;
  1555. + goto fail;
  1556. + }
  1557. +
  1558. + ssi_pdev = of_find_device_by_node(ssi_np);
  1559. + if (!ssi_pdev) {
  1560. + dev_err(&pdev->dev, "failed to find SSI platform device\n");
  1561. + ret = -EINVAL;
  1562. + goto fail;
  1563. + }
  1564. +
  1565. + codec_dev = of_find_i2c_device_by_node(codec_np);
  1566. + if (!codec_dev || !codec_dev->dev.driver) {
  1567. + dev_err(&pdev->dev, "failed to find codec platform device\n");
  1568. + ret = -EINVAL;
  1569. + goto fail;
  1570. + }
  1571. +
  1572. + data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
  1573. + if (!data) {
  1574. + ret = -ENOMEM;
  1575. + goto fail;
  1576. + }
  1577. +
  1578. + card_priv.data = data;
  1579. +
  1580. + data->codec_dev = codec_dev;
  1581. +
  1582. + data->dai.name = "HiFi";
  1583. + data->dai.stream_name = "HiFi";
  1584. + data->dai.codec_dai_name = "wm8731-hifi";
  1585. + data->dai.codec_of_node = codec_np;
  1586. + data->dai.cpu_dai_name = dev_name(&ssi_pdev->dev);
  1587. + data->dai.platform_of_node = ssi_np;
  1588. + data->dai.ops = &imx_hifi_ops;
  1589. + data->dai.init = &imx_wm8731_init;
  1590. +
  1591. + ret = of_property_read_u32(pdev->dev.of_node, "src-port", &src_port);
  1592. + if (ret) {
  1593. + dev_err(&pdev->dev, "failed to get \"src-port\" value\n");
  1594. + ret = -EINVAL;
  1595. + goto fail;
  1596. + }
  1597. +
  1598. + ret = of_property_read_u32(pdev->dev.of_node, "ext-port", &ext_port);
  1599. + if (ret) {
  1600. + dev_err(&pdev->dev, "failed to get \"ext-port\" value\n");
  1601. + ret = -EINVAL;
  1602. + goto fail;
  1603. + }
  1604. +
  1605. + ret = of_property_read_string(ssi_np, "fsl,mode", &ssi_mode_str);
  1606. + if (ret) {
  1607. + dev_err(&pdev->dev, "failed to get \"fsl,mode\" value\n");
  1608. + ret = -EINVAL;
  1609. + goto fail;
  1610. + }
  1611. +
  1612. + ssi_mode = strcmp(ssi_mode_str, "i2s-master");
  1613. +
  1614. + if (ssi_mode) {
  1615. + /* Master Mode */
  1616. + imx_audmux_config_mst_mode(src_port, ext_port);
  1617. + wm8731_mst_mode_init(data);
  1618. + data->clock_enable = wm8731_mst_mode_clock_enable;
  1619. + imx_hifi_ops.hw_params = imx_hifi_hw_params_mst_mode;
  1620. + imx_hifi_ops.startup = imx_hifi_startup_mst_mode;
  1621. + } else {
  1622. + /* Slave Mode */
  1623. + imx_audmux_config_slv_mode(src_port, ext_port);
  1624. + wm8731_slv_mode_init(data);
  1625. + data->clock_enable = wm8731_slv_mode_clock_enable;
  1626. + imx_hifi_ops.hw_params = imx_hifi_hw_params_slv_mode;
  1627. + imx_hifi_ops.startup = imx_hifi_startup_slv_mode;
  1628. + }
  1629. +
  1630. + data->card.dev = &pdev->dev;
  1631. + ret = snd_soc_of_parse_card_name(&data->card, "model");
  1632. + if (ret)
  1633. + goto fail;
  1634. +
  1635. + ret = snd_soc_of_parse_audio_routing(&data->card, "audio-routing");
  1636. + if (ret)
  1637. + goto fail;
  1638. +
  1639. + data->card.num_links = 1;
  1640. + data->card.dai_link = &data->dai;
  1641. +
  1642. + data->card.dapm_widgets = imx_dapm_widgets;
  1643. + data->card.num_dapm_widgets = ARRAY_SIZE(imx_dapm_widgets);
  1644. +
  1645. + platform_set_drvdata(pdev, &data->card);
  1646. + snd_soc_card_set_drvdata(&data->card, data);
  1647. +
  1648. + ret = devm_snd_soc_register_card(&pdev->dev, &data->card);
  1649. + if (ret) {
  1650. + dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n", ret);
  1651. + goto fail;
  1652. + }
  1653. +/* of_node_put(ssi_np);
  1654. + of_node_put(codec_np); */
  1655. + return 0;
  1656. +fail:
  1657. +
  1658. + if (ssi_np)
  1659. + of_node_put(ssi_np);
  1660. +
  1661. + if (codec_np)
  1662. + of_node_put(codec_np);
  1663. +
  1664. + return ret;
  1665. +}
  1666. +
  1667. +static int imx_wm8731_remove(struct platform_device *pdev)
  1668. +{
  1669. + struct snd_soc_card *card = platform_get_drvdata(pdev);
  1670. + snd_soc_unregister_card(card);
  1671. +
  1672. + return 0;
  1673. +}
  1674. +
  1675. +static const struct of_device_id imx_wm8731_dt_ids[] = {
  1676. + { .compatible = "fsl,imx-audio-wm8731", },
  1677. + { /* sentinel */ }
  1678. +};
  1679. +MODULE_DEVICE_TABLE(of, imx_wm8731_dt_ids);
  1680. +
  1681. +static struct platform_driver imx_wm8731_driver = {
  1682. + .driver = {
  1683. + .name = "imx-wm8731",
  1684. + .owner = THIS_MODULE,
  1685. + .of_match_table = imx_wm8731_dt_ids,
  1686. + },
  1687. + .probe = imx_wm8731_probe,
  1688. + .remove = imx_wm8731_remove,
  1689. +};
  1690. +module_platform_driver(imx_wm8731_driver);
  1691. +
  1692. +MODULE_AUTHOR("Freescale Semiconductor, Inc.");
  1693. +MODULE_DESCRIPTION("Freescale i.MX WM8731 ASoC machine driver");
  1694. +MODULE_LICENSE("GPL v2");
  1695. +MODULE_ALIAS("platform:imx-wm8731");
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