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  1. #!/bin/csh
  2. set config_dir = /proj/ABC/users/nhannguyen/work/verif/qc/input
  3. set testbench_dir = /proj/ABC/users/nhannguyen/work/verif/qc/testbench/TT_p025c
  4. bsub $testbench_dir/cell/delay_0_0.sp.py -c $config_dir/sim.config.py -m 1
  5. bsub $testbench_dir/cell/delay_0_1.sp.py -c $config_dir/sim.config.py -m 1
  6. bsub $testbench_dir/cell/delay_0_2.sp.py -c $config_dir/sim.config.py -m 1
  7. bsub $testbench_dir/cell/delay_0_3.sp.py -c $config_dir/sim.config.py -m 1
  8. bsub $testbench_dir/cell/delay_1_0.sp.py -c $config_dir/sim.config.py -m 1
  9. bsub $testbench_dir/cell/delay_1_1.sp.py -c $config_dir/sim.config.py -m 1
  10. bsub $testbench_dir/cell/delay_1_2.sp.py -c $config_dir/sim.config.py -m 1
  11. bsub $testbench_dir/cell/delay_1_3.sp.py -c $config_dir/sim.config.py -m 1
  12. ...............
  13.  
  14. #!/bin/csh
  15. set config_dir = /proj/ABC/users/nhannguyen/work/verif/qc/input
  16. set testbench_dir = /proj/ABC/users/nhannguyen/work/verif/qc/testbench/TT_p025c
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