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- => 0x01c7ecb4 <+500>: udf #65006 ; 0xfdee
- 0x01c7ecb8 <+504>: cmp r0, #0
- --Type <RET> for more, q to quit, c to continue without paging--
- 0x01c7ecbc <+508>: beq 0x1c7ecb4 <ir_analyze_async_call(IrAnalyze*, IrInst*, ZigFn*, ZigType*, IrInstGen*, IrInstGen**, unsigned int, IrInstGen*, bool, IrInstGen*, ResultLoc*)+500>
- 0x01c7ecc0 <+512>: ldr r0, [r0]
- 0x01c7ecc4 <+516>: bl 0x1bc161c <type_is_invalid(ZigType*)>
- 0x01c7ecc8 <+520>: cmp r0, #0
- 0x01c7eccc <+524>: bne 0x1c7ee50 <ir_analyze_async_call(IrAnalyze*, IrInst*, ZigFn*, ZigType*, IrInstGen*, IrInstGen**, unsigned int, IrInstGen*, bool, IrInstGen*, ResultLoc*)+912>
- 0x01c7ecd0 <+528>: ldr r0, [r7]
- 0x01c7ecd4 <+532>: tst r0, #7
- 0x01c7ecd8 <+536>: bne 0x1c7ecb4 <ir_analyze_async_call(IrAnalyze*, IrInst*, ZigFn*, ZigType*, IrInstGen*, IrInstGen**, unsigned int, IrInstGen*, bool, IrInstGen*, ResultLoc*)+500>
- 0x01c7ecdc <+540>: cmp r0, #0
- 0x01c7ece0 <+544>: beq 0x1c7ecb4 <ir_analyze_async_call(IrAnalyze*, IrInst*, ZigFn*, ZigType*, IrInstGen*, IrInstGen**, unsigned int, IrInstGen*, bool, IrInstGen*, ResultLoc*)+500>
- 0x01c7ece4 <+548>: ldr r0, [r0]
- 0x01c7ece8 <+552>: tst r0, #7
- 0x01c7ecec <+556>: bne 0x1c7ecb4 <ir_analyze_async_call(IrAnalyze*, IrInst*, ZigFn*, ZigType*, IrInstGen*, IrInstGen**, unsigned int, IrInstGen*, bool, IrInstGen*, ResultLoc*)+500>
- 0x01c7ecf0 <+560>: cmp r0, #0
- 0x01c7ecf4 <+564>: beq 0x1c7ecb4 <ir_analyze_async_call(IrAnalyze*, IrInst*, ZigFn*, ZigType*, IrInstGen*, IrInstGen**, unsigned int, IrInstGen*, bool, IrInstGen*, ResultLoc*)+500>
- 0x01c7ecf8 <+568>: ldr r0, [r0]
- 0x01c7ecfc <+572>: cmp r0, #31
- 0x01c7ed00 <+576>: bhi 0x1c7ecb4 <ir_analyze_async_call(IrAnalyze*, IrInst*, ZigFn*, ZigType*, IrInstGen*, IrInstGen**, unsigned int, IrInstGen*, bool, IrInstGen*, ResultLoc*)+500>
- 0x01c7ed04 <+580>: cmp r0, #4
- 0x01c7ed08 <+584>: beq 0x1c7ee50 <ir_analyze_async_call(IrAnalyze*, IrInst*, ZigFn*, ZigType*, IrInstGen*, IrInstGen**, unsigned int, IrInstGen*, bool, IrInstGen*, ResultLoc*)+912>
- 0x01c7ed0c <+588>: ldr r0, [r11, #32]
- 0x01c7ed10 <+592>: tst r0, #3
- 0x01c7ed14 <+596>: bne 0x1c7ecb4 <ir_analyze_async_call(IrAnalyze*, IrInst*, ZigFn*, ZigType*, IrInstGen*, IrInstGen**, unsigned int, IrInstGen*, bool, IrInstGen*, ResultLoc*)+500>
- 0x01c7ed18 <+600>: ldr r0, [r11, #32]
- 0x01c7ed1c <+604>: cmp r0, #0
- 0x01c7ed20 <+608>: beq 0x1c7ecb4 <ir_analyze_async_call(IrAnalyze*, IrInst*, ZigFn*, ZigType*, IrInstGen*, IrInstGen**, unsigned int, IrInstGen*, bool, IrInstGen*, ResultLoc*)+500>
- 0x01c7ed24 <+612>: ldr r0, [r11, #32]
- 0x01c7ed28 <+616>: add r0, r0, #12
- 0x01c7ed2c <+620>: tst r0, #3
- 0x01c7ed30 <+624>: ldreq r7, [r0]
- 0x01c7ed34 <+628>: tsteq r7, #3
- 0x01c7ed38 <+632>: bne 0x1c7ecb4 <ir_analyze_async_call(IrAnalyze*, IrInst*, ZigFn*, ZigType*, IrInstGen*, IrInstGen**, unsigned int, IrInstGen*, bool, IrInstGen*, ResultLoc*)+500>
- 0x01c7ed3c <+636>: cmp r7, #0
- 0x01c7ed40 <+640>: beq 0x1c7ecb4 <ir_analyze_async_call(IrAnalyze*, IrInst*, ZigFn*, ZigType*, IrInstGen*, IrInstGen**, unsigned int, IrInstGen*, bool, IrInstGen*, ResultLoc*)+500>
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