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- // แก้ Skill Test
- // 6031301721 Krist Pornpairin
- `timescale 1ns / 1ps
- module system(
- output[6:0] seg,
- output dp,
- output[3:0] an,
- input clk
- );
- wire an0, an1, an2, an3;
- assign an = {an0, an1, an2, an3};
- wire clk_15, clk_50;
- clockDivGen #(18) genClk1(clk_15, clk); // clock ปกติ
- clockDivGen #(27) genClk2(clk_50, clk); // clock สลับเลข
- // counter {0,1,2,3,4,0,1,2,3,4,0.....}
- reg[3:0] num;
- initial begin
- num = 0;
- end
- always @(posedge clk_50)
- begin
- num = (num + 1) % 5;
- end
- // counter ~> unary counter
- // แปลง num ให้เป็น 4 decimal digit โดยแต่ละหลักมีค่าเป็น 0 หรือ 1
- // ! warning 0 เฉยๆได้ 4'b0000 แก้บัคตรงนี้เกือบ 4 ชม :(
- wire [15:0] out;
- assign out = {
- 3'b000, num > 3,
- 3'b000, num > 2,
- 3'b000, num > 1,
- 3'b000, num > 0
- };
- // display
- quadSevenSeg q7seg(
- // output
- seg, dp,
- an0, an1, an2, an3,
- // input
- out[15:12], out[11:8], out[7:4], out[3:0],
- clk_15
- );
- endmodule
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