library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--entity AND3 is
#port (A,B,C: in STD_LOGIC;
#	F: out STD_LOGIC);
#end AND3;


#architecture BEHAVIORAL OF AND3 is
#begin
#F <=( A AND B AND C);
#end BEHAVIORAL;



#2 input not

entity NOR2 is
port (A, B: in STD_LOGIC;
	F: out STD_LOGIC);
end NOR2;

architecture behavior OF NOR2 is
begin
#F <= not(A OR B);
F <= A NOR B;
end behavior;