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  1. v3-2-4-gpu-ipu-v3-add-unsynchronised-DP-channel-disabling.patch
  2.  
  3. diff --git a/drivers/gpu/drm/imx/ipuv3-plane.c b/drivers/gpu/drm/imx/ipuv3-plane.c
  4. index 24819c9c36400..55991d46ced50 100644
  5. --- a/drivers/gpu/drm/imx/ipuv3-plane.c
  6. +++ b/drivers/gpu/drm/imx/ipuv3-plane.c
  7. @@ -181,7 +181,7 @@ static int ipu_disable_plane(struct drm_plane *plane)
  8. ipu_idmac_wait_busy(ipu_plane->ipu_ch, 50);
  9.  
  10. if (ipu_plane->dp)
  11. - ipu_dp_disable_channel(ipu_plane->dp);
  12. + ipu_dp_disable_channel(ipu_plane->dp, true);
  13. ipu_idmac_disable_channel(ipu_plane->ipu_ch);
  14. ipu_dmfc_disable_channel(ipu_plane->dmfc);
  15. if (ipu_plane->dp)
  16. diff --git a/drivers/gpu/ipu-v3/ipu-common.c b/drivers/gpu/ipu-v3/ipu-common.c
  17. index 8368e6f766ee5..8a32ed25a1c29 100644
  18. --- a/drivers/gpu/ipu-v3/ipu-common.c
  19. +++ b/drivers/gpu/ipu-v3/ipu-common.c
  20. @@ -51,15 +51,17 @@ int ipu_get_num(struct ipu_soc *ipu)
  21. }
  22. EXPORT_SYMBOL_GPL(ipu_get_num);
  23.  
  24. -void ipu_srm_dp_sync_update(struct ipu_soc *ipu)
  25. +void ipu_srm_dp_update(struct ipu_soc *ipu, bool sync)
  26. {
  27. u32 val;
  28.  
  29. val = ipu_cm_read(ipu, IPU_SRM_PRI2);
  30. - val |= 0x8;
  31. + val &= ~DP_S_SRM_MODE_MASK;
  32. + val |= sync ? DP_S_SRM_MODE_NEXT_FRAME :
  33. + DP_S_SRM_MODE_NOW;
  34. ipu_cm_write(ipu, val, IPU_SRM_PRI2);
  35. }
  36. -EXPORT_SYMBOL_GPL(ipu_srm_dp_sync_update);
  37. +EXPORT_SYMBOL_GPL(ipu_srm_dp_update);
  38.  
  39. enum ipu_color_space ipu_drm_fourcc_to_colorspace(u32 drm_fourcc)
  40. {
  41. diff --git a/drivers/gpu/ipu-v3/ipu-dp.c b/drivers/gpu/ipu-v3/ipu-dp.c
  42. index 98686edbcdbb0..0e09c98248a0d 100644
  43. --- a/drivers/gpu/ipu-v3/ipu-dp.c
  44. +++ b/drivers/gpu/ipu-v3/ipu-dp.c
  45. @@ -112,7 +112,7 @@ int ipu_dp_set_global_alpha(struct ipu_dp *dp, bool enable,
  46. writel(reg & ~DP_COM_CONF_GWAM, flow->base + DP_COM_CONF);
  47. }
  48.  
  49. - ipu_srm_dp_sync_update(priv->ipu);
  50. + ipu_srm_dp_update(priv->ipu, true);
  51.  
  52. mutex_unlock(&priv->mutex);
  53.  
  54. @@ -127,7 +127,7 @@ int ipu_dp_set_window_pos(struct ipu_dp *dp, u16 x_pos, u16 y_pos)
  55.  
  56. writel((x_pos << 16) | y_pos, flow->base + DP_FG_POS);
  57.  
  58. - ipu_srm_dp_sync_update(priv->ipu);
  59. + ipu_srm_dp_update(priv->ipu, true);
  60.  
  61. return 0;
  62. }
  63. @@ -207,7 +207,7 @@ int ipu_dp_setup_channel(struct ipu_dp *dp,
  64. flow->out_cs, DP_COM_CONF_CSC_DEF_FG);
  65. }
  66.  
  67. - ipu_srm_dp_sync_update(priv->ipu);
  68. + ipu_srm_dp_update(priv->ipu, true);
  69.  
  70. mutex_unlock(&priv->mutex);
  71.  
  72. @@ -247,7 +247,7 @@ int ipu_dp_enable_channel(struct ipu_dp *dp)
  73. reg |= DP_COM_CONF_FG_EN;
  74. writel(reg, flow->base + DP_COM_CONF);
  75.  
  76. - ipu_srm_dp_sync_update(priv->ipu);
  77. + ipu_srm_dp_update(priv->ipu, true);
  78.  
  79. mutex_unlock(&priv->mutex);
  80.  
  81. @@ -255,7 +255,7 @@ int ipu_dp_enable_channel(struct ipu_dp *dp)
  82. }
  83. EXPORT_SYMBOL_GPL(ipu_dp_enable_channel);
  84.  
  85. -void ipu_dp_disable_channel(struct ipu_dp *dp)
  86. +void ipu_dp_disable_channel(struct ipu_dp *dp, bool sync)
  87. {
  88. struct ipu_flow *flow = to_flow(dp);
  89. struct ipu_dp_priv *priv = flow->priv;
  90. @@ -275,7 +275,7 @@ void ipu_dp_disable_channel(struct ipu_dp *dp)
  91. writel(reg, flow->base + DP_COM_CONF);
  92.  
  93. writel(0, flow->base + DP_FG_POS);
  94. - ipu_srm_dp_sync_update(priv->ipu);
  95. + ipu_srm_dp_update(priv->ipu, sync);
  96.  
  97. if (ipu_idmac_channel_busy(priv->ipu, IPUV3_CHANNEL_MEM_BG_SYNC))
  98. ipu_wait_interrupt(priv->ipu, IPU_IRQ_DP_SF_END, 50);
  99. diff --git a/drivers/gpu/ipu-v3/ipu-prv.h b/drivers/gpu/ipu-v3/ipu-prv.h
  100. index 22e47b68b14a2..285595702ee0f 100644
  101. --- a/drivers/gpu/ipu-v3/ipu-prv.h
  102. +++ b/drivers/gpu/ipu-v3/ipu-prv.h
  103. @@ -75,6 +75,11 @@ struct ipu_soc;
  104. #define IPU_INT_CTRL(n) IPU_CM_REG(0x003C + 4 * (n))
  105. #define IPU_INT_STAT(n) IPU_CM_REG(0x0200 + 4 * (n))
  106.  
  107. +/* SRM_PRI2 */
  108. +#define DP_S_SRM_MODE_MASK (0x3 << 3)
  109. +#define DP_S_SRM_MODE_NOW (0x3 << 3)
  110. +#define DP_S_SRM_MODE_NEXT_FRAME (0x1 << 3)
  111. +
  112. /* FS_PROC_FLOW1 */
  113. #define FS_PRPENC_ROT_SRC_SEL_MASK (0xf << 0)
  114. #define FS_PRPENC_ROT_SRC_SEL_ENC (0x7 << 0)
  115. @@ -215,7 +220,7 @@ static inline void ipu_idmac_write(struct ipu_soc *ipu, u32 value,
  116. writel(value, ipu->idmac_reg + offset);
  117. }
  118.  
  119. -void ipu_srm_dp_sync_update(struct ipu_soc *ipu);
  120. +void ipu_srm_dp_update(struct ipu_soc *ipu, bool sync);
  121.  
  122. int ipu_module_enable(struct ipu_soc *ipu, u32 mask);
  123. int ipu_module_disable(struct ipu_soc *ipu, u32 mask);
  124. diff --git a/include/video/imx-ipu-v3.h b/include/video/imx-ipu-v3.h
  125. index 53cd07ccaa4ce..899d2b00ad6d4 100644
  126. --- a/include/video/imx-ipu-v3.h
  127. +++ b/include/video/imx-ipu-v3.h
  128. @@ -300,7 +300,7 @@ struct ipu_dp *ipu_dp_get(struct ipu_soc *ipu, unsigned int flow);
  129. void ipu_dp_put(struct ipu_dp *);
  130. int ipu_dp_enable(struct ipu_soc *ipu);
  131. int ipu_dp_enable_channel(struct ipu_dp *dp);
  132. -void ipu_dp_disable_channel(struct ipu_dp *dp);
  133. +void ipu_dp_disable_channel(struct ipu_dp *dp, bool sync);
  134. void ipu_dp_disable(struct ipu_soc *ipu);
  135. int ipu_dp_setup_channel(struct ipu_dp *dp,
  136. enum ipu_color_space in, enum ipu_color_space out);
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