dd

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity Delay_gen is
  generic(
    clk_speed        : integer := 50_000_000;
    delay_multiplier : integer := 100);  --100 is 100Khz(max in normal operation). 25 is max in fastmode ( 400Khz). >100 is less Hz
  port (clock_50 : in  std_logic;
        resetn   : in  std_logic;
        T        : out std_logic;  -- sender ut T når klokken har telt clk_speed/i2c_speed ganger.
        ENABLE   : in  std_logic);
end;

architecture rtl of Delay_gen is

  constant delay : integer := ((5*delay_multiplier)/clk_speed);
  signal teller  : integer := 0;

begin
  -- teller til clk_speed/i2c_speed som er en fast delay mellom endring av signaler
  process(clock_50) is
  begin
    if rising_edge(clock_50) then
      if (resetn = '0' or ENABLE = '1') then
        teller <= 0;
      else
        teller <= teller +1;
        if teller = delay then
          T      <= '1';
          teller <= 0;
        else
          T <= '0';
        end if;
      end if;
    end if;
  end process;
end;