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- sfx@tinker:~$ uname -a
- Linux tinker 4.14.67-rockchip #88 SMP PREEMPT Wed Aug 29 15:07:29 CEST 2018 armv7l armv7l armv7l GNU/Linux
- sfx@tinker:~$ lscpu
- Architecture: armv7l
- Byte Order: Little Endian
- CPU(s): 4
- On-line CPU(s) list: 0-3
- Thread(s) per core: 1
- Core(s) per socket: 4
- Socket(s): 1
- Vendor ID: ARM
- Model: 1
- Model name: Cortex-A12
- Stepping: r0p1
- CPU max MHz: 1800.0000
- CPU min MHz: 600.0000
- BogoMIPS: 172.80
- Flags: half thumb fastmult vfp edsp thumbee neon vfpv3 tls vfpv4 idiva idivt vfpd32 lpae evtstrm
- sfx@tinker:~/builds/tinymembench$ sudo cpufreq-set -g performance
- sfx@tinker:~/builds/tinymembench$ ./tinymembench
- tinymembench v0.4.9 (simple benchmark for memory throughput and latency)
- ==========================================================================
- == Memory bandwidth tests ==
- == ==
- == Note 1: 1MB = 1000000 bytes ==
- == Note 2: Results for 'copy' tests show how many bytes can be ==
- == copied per second (adding together read and writen ==
- == bytes would have provided twice higher numbers) ==
- == Note 3: 2-pass copy means that we are using a small temporary buffer ==
- == to first fetch data into it, and only then write it to the ==
- == destination (source -> L1 cache, L1 cache -> destination) ==
- == Note 4: If sample standard deviation exceeds 0.1%, it is shown in ==
- == brackets ==
- ==========================================================================
- C copy backwards : 2229.4 MB/s (1.4%)
- C copy backwards (32 byte blocks) : 2243.3 MB/s (1.5%)
- C copy backwards (64 byte blocks) : 2245.4 MB/s (0.6%)
- C copy : 2445.6 MB/s (0.3%)
- C copy prefetched (32 bytes step) : 2126.2 MB/s (0.2%)
- C copy prefetched (64 bytes step) : 2177.2 MB/s (0.2%)
- C 2-pass copy : 1447.5 MB/s
- C 2-pass copy prefetched (32 bytes step) : 1447.0 MB/s (0.2%)
- C 2-pass copy prefetched (64 bytes step) : 1447.2 MB/s
- C fill : 4059.9 MB/s (0.1%)
- C fill (shuffle within 16 byte blocks) : 4048.6 MB/s
- C fill (shuffle within 32 byte blocks) : 4102.3 MB/s (0.4%)
- C fill (shuffle within 64 byte blocks) : 4056.6 MB/s
- ---
- standard memcpy : 1608.6 MB/s
- standard memset : 4052.6 MB/s (2.3%)
- ---
- NEON read : 4869.7 MB/s (13.3%)
- NEON read prefetched (32 bytes step) : 4348.8 MB/s (5.7%)
- NEON read prefetched (64 bytes step) : 4473.0 MB/s (4.2%)
- NEON read 2 data streams : 4639.6 MB/s (6.1%)
- NEON read 2 data streams prefetched (32 bytes step) : 4017.6 MB/s (3.1%)
- NEON read 2 data streams prefetched (64 bytes step) : 3924.3 MB/s (4.2%)
- NEON copy : 2437.7 MB/s (0.9%)
- NEON copy prefetched (32 bytes step) : 1784.0 MB/s (1.7%)
- NEON copy prefetched (64 bytes step) : 1782.1 MB/s (2.0%)
- NEON unrolled copy : 2467.9 MB/s (2.4%)
- NEON unrolled copy prefetched (32 bytes step) : 2040.3 MB/s (1.3%)
- NEON unrolled copy prefetched (64 bytes step) : 2442.2 MB/s (3.1%)
- NEON copy backwards : 2567.5 MB/s (2.5%)
- NEON copy backwards prefetched (32 bytes step) : 2289.2 MB/s (2.8%)
- NEON copy backwards prefetched (64 bytes step) : 1794.4 MB/s (3.3%)
- NEON 2-pass copy : 1352.5 MB/s (3.0%)
- NEON 2-pass copy prefetched (32 bytes step) : 1340.2 MB/s (2.8%)
- NEON 2-pass copy prefetched (64 bytes step) : 1140.7 MB/s (2.4%)
- NEON unrolled 2-pass copy : 1373.5 MB/s (3.7%)
- NEON unrolled 2-pass copy prefetched (32 bytes step) : 1323.3 MB/s (3.1%)
- NEON unrolled 2-pass copy prefetched (64 bytes step) : 1424.1 MB/s (7.2%)
- NEON fill : 4011.8 MB/s (4.9%)
- NEON fill backwards : 4029.3 MB/s (2.0%)
- VFP copy : 2352.5 MB/s (5.2%)
- VFP 2-pass copy : 1381.0 MB/s (2.5%)
- ARM fill (STRD) : 3949.9 MB/s (2.0%)
- ARM fill (STM with 8 registers) : 3994.7 MB/s (3.5%)
- ARM fill (STM with 4 registers) : 3976.2 MB/s (0.9%)
- ARM copy prefetched (incr pld) : 2228.7 MB/s (6.7%)
- ARM copy prefetched (wrap pld) : 2195.4 MB/s (3.0%)
- ARM 2-pass copy prefetched (incr pld) : 1324.0 MB/s (6.4%)
- ARM 2-pass copy prefetched (wrap pld) : 1255.2 MB/s (8.3%)
- ==========================================================================
- == Memory latency test ==
- == ==
- == Average time is measured for random memory accesses in the buffers ==
- == of different sizes. The larger is the buffer, the more significant ==
- == are relative contributions of TLB, L1/L2 cache misses and SDRAM ==
- == accesses. For extremely large buffer sizes we are expecting to see ==
- == page table walk with several requests to SDRAM for almost every ==
- == memory access (though 64MiB is not nearly large enough to experience ==
- == this effect to its fullest). ==
- == ==
- == Note 1: All the numbers are representing extra time, which needs to ==
- == be added to L1 cache latency. The cycle timings for L1 cache ==
- == latency can be usually found in the processor documentation. ==
- == Note 2: Dual random read means that we are simultaneously performing ==
- == two independent memory accesses at a time. In the case if ==
- == the memory subsystem can't handle multiple outstanding ==
- == requests, dual random read has the same timings as two ==
- == single reads performed one after another. ==
- ==========================================================================
- block size : single random read / dual random read
- 1024 : 0.2 ns / 0.0 ns
- 2048 : 0.4 ns / 0.0 ns
- 4096 : 0.0 ns / 0.0 ns
- 8192 : 0.0 ns / 0.0 ns
- 16384 : 0.0 ns / 0.0 ns
- 32768 : 0.0 ns / 0.0 ns
- 65536 : 5.6 ns / 9.5 ns
- 131072 : 8.7 ns / 14.2 ns
- 262144 : 13.1 ns / 18.2 ns
- 524288 : 13.2 ns / 18.0 ns
- 1048576 : 21.5 ns / 26.4 ns
- 2097152 : 72.5 ns / 107.7 ns
- 4194304 : 100.6 ns / 136.1 ns
- 8388608 : 119.4 ns / 151.9 ns
- 16777216 : 131.8 ns / 163.5 ns
- 33554432 : 141.3 ns / 171.0 ns
- 67108864 : 149.9 ns / 182.1 ns
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