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  1. # clktst.py - checkout clock domains
  2. # 2020-08-06 E. Brombaugh
  3.  
  4. from nmigen import *
  5. from nmigen.sim.pysim import *
  6.  
  7. # simple counter for submodules
  8. class counter(Elaboratable):
  9.     def __init__(self):        
  10.         # ports
  11.         self.output = Signal(4)
  12.        
  13.     def elaborate(self, platform):
  14.         m = Module()
  15.        
  16.         m.d.sync += self.output.eq(self.output + 1)
  17.        
  18.         return m        
  19.  
  20. # hook up some counters in different domains
  21. class clktst(Elaboratable):
  22.     def __init__(self):        
  23.         # ports
  24.         self.out1 = Signal(4)
  25.         self.out2 = Signal(4)
  26.        
  27.     def elaborate(self, platform):
  28.         m = Module()
  29.        
  30.         # generate lower rate clk
  31.         clk_div2 = Signal()
  32.         m.d.sync += clk_div2.eq(~clk_div2)
  33.        
  34.         # instantiate first counter at default rate
  35.         m.submodules.cnt1 = counter()
  36.        
  37.         # instantiate second counter with rename
  38.         m.submodules.cnt2 = DomainRenamer("sync_two")(counter())
  39.        
  40.         # create a clock domain in the renamed domain and connect to divided clock
  41.         sync2 = ClockDomain("sync_two")
  42.         m.domains += sync2
  43.         m.d.comb += sync2.clk.eq(clk_div2)
  44.        
  45.         # route both counters out
  46.         m.d.comb += [
  47.             self.out1.eq(m.submodules.cnt1.output),
  48.             self.out2.eq(m.submodules.cnt2.output)
  49.         ]
  50.        
  51.         return m
  52.  
  53. # simulate
  54. if __name__ == "__main__":
  55.     dut = clktst()
  56.     sim = Simulator(dut)
  57.     with sim.write_vcd("clktst.vcd"):
  58.         def proc():
  59.             for i in range( 256 ):                    
  60.                 yield Tick()
  61.         sim.add_clock( 1/40e6 )
  62.         sim.add_sync_process( proc )
  63.         sim.run()
  64.  
  65.  
  66.  
  67.  
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