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ZirconiumX Jun 22nd, 2019 93 Never
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  1. module sh4a_regfile(
  2.     input clk,
  3.     input reset,
  4.  
  5.     output [31:0] program_counter,
  6.  
  7.     input [4:0] int_idx_read0_pipe0,
  8.     input [4:0] int_idx_read1_pipe0,
  9.     input [4:0] int_idx_write_pipe0,
  10.     input [31:0] int_reg_write_pipe0,
  11.     input int_reg_write_enable_pipe0,
  12.     output reg [31:0] int_reg_read0_pipe0,
  13.     output reg [31:0] int_reg_read1_pipe0,
  14.  
  15.     input [4:0] int_idx_read0_pipe1,
  16.     input [4:0] int_idx_read1_pipe1,
  17.     input [4:0] int_idx_write_pipe1,
  18.     input [31:0] int_reg_write_pipe1,
  19.     input int_reg_write_enable_pipe1,
  20.     output reg [31:0] int_reg_read0_pipe1,
  21.     output reg [31:0] int_reg_read1_pipe1
  22. );
  23.  
  24. localparam REG0_BANK0   = 5'd0;
  25. localparam REG1_BANK0   = 5'd1;
  26. localparam REG2_BANK0   = 5'd2;
  27. localparam REG3_BANK0   = 5'd3;
  28. localparam REG4_BANK0   = 5'd4;
  29. localparam REG5_BANK0   = 5'd5;
  30. localparam REG6_BANK0   = 5'd6;
  31. localparam REG7_BANK0   = 5'd7;
  32. localparam REG8         = 5'd8;
  33. localparam REG9         = 5'd9;
  34. localparam REG10        = 5'd10;
  35. localparam REG11        = 5'd11;
  36. localparam REG12        = 5'd12;
  37. localparam REG13        = 5'd13;
  38. localparam REG14        = 5'd14;
  39. localparam REG15        = 5'd15;
  40. localparam REG0_BANK1   = 5'd16;
  41. localparam REG1_BANK1   = 5'd17;
  42. localparam REG2_BANK1   = 5'd18;
  43. localparam REG3_BANK1   = 5'd19;
  44. localparam REG4_BANK1   = 5'd20;
  45. localparam REG5_BANK1   = 5'd21;
  46. localparam REG6_BANK1   = 5'd21;
  47. localparam REG7_BANK1   = 5'd23;
  48.  
  49. localparam RESET_PC     = 32'hA000_0000;
  50.  
  51. reg [31:0] program_counter_register;
  52. reg [31:0] int_registers [0:31];
  53.  
  54. `ifdef FORMAL
  55. // Always start with a high reset line.
  56. initial @($global_clock) begin
  57.     restrict(reset);
  58. end
  59. `endif
  60.  
  61. always @(posedge clk) begin
  62. `ifdef FORMAL
  63.     // The clock always ticks.
  64.     assume(clk == !$past(clk));
  65.  
  66.     // We must never access an invalid register.
  67.     assert(int_idx_read0_pipe0 >= 0 && int_idx_read0_pipe0 <= 23);
  68.     assert(int_idx_read1_pipe0 >= 0 && int_idx_read1_pipe0 <= 23);
  69.     assert(int_idx_write_pipe0 >= 0 && int_idx_write_pipe0 <= 23);
  70.  
  71.     assert(int_idx_read0_pipe1 >= 0 && int_idx_read0_pipe1 <= 23);
  72.     assert(int_idx_read1_pipe1 >= 0 && int_idx_read1_pipe1 <= 23);
  73.     assert(int_idx_write_pipe1 >= 0 && int_idx_write_pipe1 <= 23);
  74.  
  75.     // Pipes must not try to write to the same register at the same time.
  76.     assert(int_idx_write_pipe0 != int_idx_write_pipe1);
  77. `endif
  78.  
  79.     if (reset) begin
  80.         program_counter_register <= RESET_PC;
  81.     end else begin
  82.         if (int_reg_write_enable_pipe0)
  83.             int_registers[int_idx_write_pipe0] <= int_reg_write_pipe0;
  84.  
  85.         int_reg_read0_pipe0 <= int_registers[int_idx_read0_pipe0];
  86.         int_reg_read1_pipe0 <= int_registers[int_idx_read1_pipe0];
  87.  
  88.         /*if (int_reg_write_enable_pipe1)
  89.             int_registers[int_idx_write_pipe1] <= int_reg_write_pipe1;
  90.  
  91.         int_reg_read0_pipe1 <= int_registers[int_idx_read0_pipe1];
  92.         int_reg_read1_pipe1 <= int_registers[int_idx_read1_pipe1];*/
  93.     end
  94. end
  95.  
  96. assign program_counter = program_counter_register;
  97.  
  98. endmodule
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