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shmem dtsi configuration

botsnlinux
Apr 9th, 2018
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  1. /include/ "system-conf.dtsi"
  2. #include <dt-bindings/phy/phy.h>
  3.  
  4. / {
  5. model = "Avnet UltraZed-3EG";
  6. chosen {
  7. bootargs = "earlycon=cdns,mmio,0xFF000000,115200n8 root=/dev/mmcblk1p2 rw rootwait earlyprintk clk_ignore_unused cma=512m";
  8. };
  9.  
  10. /* Stuff for using the R5 with remoteproc
  11. * Copied from Xilinx wiki: http://www.wiki.xilinx.com/OpenAMP+2017.2
  12. */
  13. reserved-memory {
  14. #address-cells = <2>;
  15. #size-cells = <2>;
  16. ranges;
  17. rproc_0_reserved: rproc@3ed000000 {
  18. no-map;
  19. /* DDR memory reserved for RPU firmware.
  20. * If you want to use predefined shared memory,
  21. * you should also reserved them here.
  22. */
  23. reg = <0x0 0x3ed00000 0x0 0x1000000>;
  24. };
  25. };
  26.  
  27. power-domains {
  28. /* For TCM memories, you will need specify the power domain
  29. * IDs. As APU will need to use the power domain ID to request
  30. * access through PMU FW.
  31. */
  32. pd_r5_0: pd_r5_0 {
  33. #power-domain-cells = <0x0>;
  34. pd-id = <0x7>;
  35. };
  36. pd_tcm_0_a: pd_tcm_0_a {
  37. #power-domain-cells = <0x0>;
  38. pd-id = <0xf>;
  39. };
  40. pd_tcm_0_b: pd_tcm_0_b {
  41. #power-domain-cells = <0x0>;
  42. pd-id = <0x10>;
  43. };
  44.  
  45. };
  46.  
  47. amba {
  48. /* You will need to specify the firmware memory as "mmio-sram". */
  49. r5_0_tcm_a: tcm@ffe00000 {
  50. compatible = "mmio-sram";
  51. reg = <0 0xFFE00000 0x0 0x10000>;
  52. pd-handle = <&pd_tcm_0_a>;
  53. };
  54. r5_0_tcm_b: tcm@ffe20000 {
  55. compatible = "mmio-sram";
  56. reg = <0 0xFFE20000 0x0 0x10000>;
  57. pd-handle = <&pd_tcm_0_b>;
  58. };
  59.  
  60. /* DRAM reserved for executable
  61. * the address must match the reserved memory section above */
  62. elf_ddr_0: ddr@3ed00000 {
  63. compatible = "mmio-sram";
  64. reg = <0 0x3ed00000 0x0 0x100000>;
  65. };
  66.  
  67. /* And finally the actual remoteproc entry */
  68. /* This is for 2017.2; note that there are some small (but critical)
  69. * changes in 2017.3 */
  70. test_r50: zynqmp_r5_rproc@0 {
  71. compatible = "xlnx,zynqmp-r5-remoteproc-1.0";
  72. reg = <0x0 0xff9a0100 0 0x100>, <0x0 0xff340000 0 0x100>, <0x0 0xff9a0000 0 0x100>;
  73. reg-names = "rpu_base", "ipi", "rpu_glbl_base";
  74. dma-ranges;
  75. core_conf = "split0";
  76.  
  77. /* Specify the firmware memories here */
  78. sram_0 = <&r5_0_tcm_a>;
  79. sram_1 = <&r5_0_tcm_b>;
  80. sram_2 = <&elf_ddr_0>;
  81. pd-handle = <&pd_r5_0>;
  82. interrupt-parent = <&gic>;
  83. interrupts = <0 29 4>;
  84. } ;
  85.  
  86. };
  87.  
  88. /* END of R5 remoteproc stuff */
  89.  
  90. };
  91. /* END of root node; everything below is a reference to something that already
  92. * exists in the tree. */
  93.  
  94.  
  95. /* Ethernet config for production silicon */
  96. //&gem3 {
  97. // status = "okay";
  98. // local-mac-address = [00 0a 35 00 02 90];
  99. // phy-mode = "rgmii-id";
  100. // phy-handle = <&phy0>;
  101. // phy0: phy@9 {
  102. // reg = <0x9>;
  103. // ti,rx-internal-delay = <0x5>;
  104. // ti,tx-internal-delay = <0x5>;
  105. // ti,fifo-depth = <0x1>;
  106. // };
  107. //};
  108.  
  109. /* Ethernet for ES1 silicon */
  110. &gem3 {
  111. status = "okay";
  112. local-mac-address = [00 0a 35 00 02 90];
  113. phy-mode = "rgmii-id";
  114. phy-handle = <&phy0>;
  115. phy0: phy@5 {
  116. reg = <0x5>;
  117. ti,rx-internal-delay = <0x5>;
  118. ti,tx-internal-delay = <0x5>;
  119. ti,fifo-depth = <0x1>;
  120. };
  121. };
  122.  
  123. // Hard I2C controller and the DP clock generator connected to it
  124. &i2c1 {
  125. status = "okay";
  126. clock-frequency = <400000>;
  127. i2cswitch@70 { /* u7 */
  128. compatible = "nxp,pca9543";
  129. #address-cells = <1>;
  130. #size-cells = <0>;
  131. reg = <0x70>;
  132. i2c@0 { /* i2c mw 70 0 1 */
  133. #address-cells = <1>;
  134. #size-cells = <0>;
  135. reg = <0>;
  136. // TODO: the other board has an eeprom@52 (U5 on IOCC)?
  137. eeprom: eeprom1@50 { /* 2048-bit (8-bit X 256) IIC_EEPROM - SOM U8 */
  138. compatible = "at,24c02";
  139. reg = <0x50>;
  140. };
  141.  
  142. macid: eeprom2@51 { /* IIC_MAC_ID - IOCC U5 */
  143. compatible = "at,24mac402";
  144. reg = <0x51>;
  145. };
  146.  
  147. idt5901: clock-generator@6a { /* IDT 5P49V5935 clock generator - IOCC U1 */
  148. #clock-cells = <0>;
  149. compatible = "idt,idt5901";
  150. reg = <0x6a>;
  151. input-freq = <25000000>;
  152. clk-freq = <75000000>;
  153. output-num = <4>;
  154. };
  155. };
  156. i2c@1 { /* i2c mw 70 0 2 */
  157. #address-cells = <1>;
  158. #size-cells = <0>;
  159. reg = <1>;
  160. /* SMBUS */
  161. };
  162. };
  163. };
  164.  
  165. &qspi {
  166. #address-cells = <1>;
  167. #size-cells = <0>;
  168. status = "okay";
  169. flash0: flash@0 {
  170. compatible = "micron,n25q256a"; /* 32MB */
  171. #address-cells = <1>;
  172. #size-cells = <1>;
  173. reg = <0x0>;
  174. spi-tx-bus-width = <1>;
  175. spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
  176. spi-max-frequency = <108000000>; /* Based on DC1 spec */
  177. partition@qspi-boot {
  178. label = "qspi-boot";
  179. reg = <0x0 0x780000>;
  180. };
  181. partition@qspi-bootenv {
  182. label = "qspi-bootenv";
  183. reg = <0x780000 0x80000>;
  184. };
  185. partition@qspi-linux {
  186. label = "qspi-linux";
  187. reg = <0x800000 0x3800000>;
  188. };
  189. };
  190. };
  191.  
  192. /* SD0 eMMC, 8-bit wide data bus */
  193. &sdhci0 {
  194. status = "okay";
  195. bus-width = <8>;
  196. clock-frequency = <199998006>;
  197. max-frequency = <50000000>;
  198. };
  199.  
  200. /* SD1 with level shifter */
  201. &sdhci1 {
  202. status = "okay";
  203. no-1-8-v; /* for 1.0 silicon */
  204. xlnx,mio_bank = <1>;
  205. disable-wp;
  206. };
  207.  
  208. /* ULPI SMSC USB3320 */
  209. &usb0 {
  210. status = "okay";
  211. };
  212.  
  213. &dwc3_0 {
  214. status = "okay";
  215. dr_mode = "host";
  216. phy-names = "usb3-phy";
  217. };
  218.  
  219. /* DisplayPort Configuration */
  220. &xilinx_drm {
  221. status = "okay";
  222. clocks = <&idt5901>;
  223. xlnx,vid-clk-pl;
  224. planes {
  225. xlnx,pixel-format = "argb8888";
  226. };
  227. };
  228.  
  229. &xlnx_dp {
  230. status = "okay";
  231. phy-names = "dp-phy0", "dp-phy1";
  232. phys = <&lane3 PHY_TYPE_DP 0 3 27000000>;
  233. };
  234.  
  235. &xlnx_dp_sub {
  236. status = "okay";
  237. xlnx,vid-clk-pl;
  238. xlnx,gfx-fmt = "argb8888";
  239. };
  240.  
  241. &xlnx_dp_snd_card {
  242. status = "okay";
  243. };
  244.  
  245. &xlnx_dp_snd_codec0 {
  246. status = "okay";
  247. };
  248.  
  249. &xlnx_dp_snd_pcm0 {
  250. status = "okay";
  251. };
  252.  
  253. &xlnx_dp_snd_pcm1 {
  254. status = "okay";
  255. };
  256.  
  257. &xlnx_dpdma {
  258. status = "okay";
  259. };
  260. /* END DisplayPort config */
  261.  
  262. /* Turn all the fabric clocks on, because petalinux tries to turn them off
  263. * to save power. */
  264. &clkc {
  265. fclk-enable = <0xf>;
  266. };
  267.  
  268. &fclk0 {
  269. status = "okay";
  270. };
  271.  
  272. &fclk1 {
  273. status = "okay";
  274. };
  275.  
  276. &fclk2 {
  277. status = "okay";
  278. };
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