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mt7628an.dtsi

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Jul 14th, 2017
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  1. / {
  2. #address-cells = <1>;
  3. #size-cells = <1>;
  4. compatible = "ralink,mtk7628an-soc";
  5.  
  6. cpus {
  7. cpu@0 {
  8. compatible = "mips,mips24KEc";
  9. };
  10. };
  11.  
  12. chosen {
  13. bootargs = "console=ttyS0,57600";
  14. };
  15.  
  16. aliases {
  17. serial0 = &uartlite;
  18. };
  19.  
  20. cpuintc: cpuintc@0 {
  21. #address-cells = <0>;
  22. #interrupt-cells = <1>;
  23. interrupt-controller;
  24. compatible = "mti,cpu-interrupt-controller";
  25. };
  26.  
  27. palmbus: palmbus@10000000 {
  28. compatible = "palmbus";
  29. reg = <0x10000000 0x200000>;
  30. ranges = <0x0 0x10000000 0x1FFFFF>;
  31.  
  32. #address-cells = <1>;
  33. #size-cells = <1>;
  34.  
  35. sysc: sysc@0 {
  36. compatible = "ralink,mt7620a-sysc";
  37. reg = <0x0 0x100>;
  38. };
  39.  
  40. watchdog: watchdog@120 {
  41. compatible = "ralink,mt7628an-wdt", "mtk,mt7621-wdt";
  42. reg = <0x120 0x10>;
  43.  
  44. resets = <&rstctrl 8>;
  45. reset-names = "wdt";
  46.  
  47. interrupt-parent = <&intc>;
  48. interrupts = <24>;
  49. };
  50.  
  51. intc: intc@200 {
  52. compatible = "ralink,mt7628an-intc", "ralink,rt2880-intc";
  53. reg = <0x200 0x100>;
  54.  
  55. resets = <&rstctrl 9>;
  56. reset-names = "intc";
  57.  
  58. interrupt-controller;
  59. #interrupt-cells = <1>;
  60.  
  61. interrupt-parent = <&cpuintc>;
  62. interrupts = <2>;
  63.  
  64. ralink,intc-registers = <0x9c 0xa0
  65. 0x6c 0xa4
  66. 0x80 0x78>;
  67. };
  68.  
  69. memc: memc@300 {
  70. compatible = "ralink,mt7620a-memc", "ralink,rt3050-memc";
  71. reg = <0x300 0x100>;
  72.  
  73. resets = <&rstctrl 20>;
  74. reset-names = "mc";
  75.  
  76. interrupt-parent = <&intc>;
  77. interrupts = <3>;
  78. };
  79.  
  80. gpio@600 {
  81. #address-cells = <1>;
  82. #size-cells = <0>;
  83.  
  84. compatible = "mtk,mt7628-gpio", "mtk,mt7621-gpio";
  85. reg = <0x600 0x100>;
  86.  
  87. interrupt-parent = <&intc>;
  88. interrupts = <6>;
  89.  
  90. gpio0: bank@0 {
  91. reg = <0>;
  92. compatible = "mtk,mt7621-gpio-bank";
  93. gpio-controller;
  94. #gpio-cells = <2>;
  95. };
  96.  
  97. gpio1: bank@1 {
  98. reg = <1>;
  99. compatible = "mtk,mt7621-gpio-bank";
  100. gpio-controller;
  101. #gpio-cells = <2>;
  102. };
  103.  
  104. gpio2: bank@2 {
  105. reg = <2>;
  106. compatible = "mtk,mt7621-gpio-bank";
  107. gpio-controller;
  108. #gpio-cells = <2>;
  109. };
  110. };
  111.  
  112. i2c: i2c@900 {
  113. compatible = "mediatek,mt7621-i2c";
  114. reg = <0x900 0x100>;
  115.  
  116. resets = <&rstctrl 16>;
  117. reset-names = "i2c";
  118.  
  119. #address-cells = <1>;
  120. #size-cells = <0>;
  121.  
  122. status = "disabled";
  123.  
  124. pinctrl-names = "default";
  125. pinctrl-0 = <&i2c_pins>;
  126. };
  127.  
  128. i2s: i2s@a00 {
  129. compatible = "mediatek,mt7628-i2s";
  130. reg = <0xa00 0x100>;
  131.  
  132. resets = <&rstctrl 17>;
  133. reset-names = "i2s";
  134.  
  135. interrupt-parent = <&intc>;
  136. interrupts = <10>;
  137.  
  138. txdma-req = <2>;
  139. rxdma-req = <3>;
  140.  
  141. dmas = <&gdma 4>,
  142. <&gdma 6>;
  143. dma-names = "tx", "rx";
  144.  
  145. status = "disabled";
  146. };
  147.  
  148. spi0: spi@b00 {
  149. compatible = "ralink,mt7621-spi";
  150. reg = <0xb00 0x100>;
  151.  
  152. resets = <&rstctrl 18>;
  153. reset-names = "spi";
  154.  
  155. #address-cells = <1>;
  156. #size-cells = <0>;
  157.  
  158. pinctrl-names = "default";
  159. pinctrl-0 = <&spi_pins>;
  160.  
  161. status = "disabled";
  162. };
  163.  
  164. uartlite: uartlite@c00 {
  165. compatible = "ns16550a";
  166. reg = <0xc00 0x100>;
  167.  
  168. reg-shift = <2>;
  169. reg-io-width = <4>;
  170. no-loopback-test;
  171.  
  172. clock-frequency = <40000000>;
  173.  
  174. resets = <&rstctrl 12>;
  175. reset-names = "uartl";
  176.  
  177. interrupt-parent = <&intc>;
  178. interrupts = <20>;
  179.  
  180. pinctrl-names = "default";
  181. pinctrl-0 = <&uart0_pins>;
  182. };
  183.  
  184. uart1: uart1@d00 {
  185. compatible = "ns16550a";
  186. reg = <0xd00 0x100>;
  187.  
  188. reg-shift = <2>;
  189. reg-io-width = <4>;
  190. no-loopback-test;
  191.  
  192. clock-frequency = <40000000>;
  193.  
  194. resets = <&rstctrl 19>;
  195. reset-names = "uart1";
  196.  
  197. interrupt-parent = <&intc>;
  198. interrupts = <21>;
  199.  
  200. pinctrl-names = "default";
  201. pinctrl-0 = <&uart1_pins>;
  202.  
  203. status = "disabled";
  204. };
  205.  
  206. uart2: uart2@e00 {
  207. compatible = "ns16550a";
  208. reg = <0xe00 0x100>;
  209.  
  210. reg-shift = <2>;
  211. reg-io-width = <4>;
  212. no-loopback-test;
  213.  
  214. clock-frequency = <40000000>;
  215.  
  216. resets = <&rstctrl 20>;
  217. reset-names = "uart2";
  218.  
  219. interrupt-parent = <&intc>;
  220. interrupts = <22>;
  221.  
  222. pinctrl-names = "default";
  223. pinctrl-0 = <&uart2_pins>;
  224.  
  225. status = "disabled";
  226. };
  227.  
  228. pwm: pwm@5000 {
  229. compatible = "mediatek,mt7628-pwm";
  230. reg = <0x5000 0x1000>;
  231.  
  232. resets = <&rstctrl 31>;
  233. reset-names = "pwm";
  234.  
  235. pinctrl-names = "default";
  236. pinctrl-0 = <&pwm0_pins>, <&pwm1_pins>;
  237.  
  238. interrupt-parent = <&intc>;
  239. interrupts = <26>;
  240.  
  241. status = "disabled";
  242. };
  243.  
  244. pcm: pcm@2000 {
  245. compatible = "ralink,mt7620a-pcm";
  246. reg = <0x2000 0x800>;
  247.  
  248. resets = <&rstctrl 11>;
  249. reset-names = "pcm";
  250.  
  251. interrupt-parent = <&intc>;
  252. interrupts = <4>;
  253.  
  254. status = "disabled";
  255. };
  256.  
  257. gdma: gdma@2800 {
  258. compatible = "ralink,rt3883-gdma";
  259. reg = <0x2800 0x800>;
  260.  
  261. resets = <&rstctrl 14>;
  262. reset-names = "dma";
  263.  
  264. interrupt-parent = <&intc>;
  265. interrupts = <7>;
  266.  
  267. #dma-cells = <1>;
  268. #dma-channels = <16>;
  269. #dma-requests = <16>;
  270.  
  271. status = "disabled";
  272. };
  273. };
  274.  
  275. pinctrl: pinctrl {
  276. compatible = "ralink,rt2880-pinmux";
  277. pinctrl-names = "default";
  278. pinctrl-0 = <&state_default>;
  279.  
  280. state_default: pinctrl0 {
  281. };
  282.  
  283. spi_pins: spi {
  284. spi {
  285. ralink,group = "spi";
  286. ralink,function = "spi";
  287. };
  288. };
  289.  
  290. spi_cs1_pins: spi_cs1 {
  291. spi_cs1 {
  292. ralink,group = "spi cs1";
  293. ralink,function = "spi cs1";
  294. };
  295. };
  296.  
  297. i2c_pins: i2c {
  298. i2c {
  299. ralink,group = "i2c";
  300. ralink,function = "i2c";
  301. };
  302. };
  303.  
  304. uart0_pins: uartlite {
  305. uartlite {
  306. ralink,group = "uart0";
  307. ralink,function = "uart0";
  308. };
  309. };
  310.  
  311. uart1_pins: uart1 {
  312. uart1 {
  313. ralink,group = "uart1";
  314. ralink,function = "uart1";
  315. };
  316. };
  317.  
  318. uart2_pins: uart2 {
  319. uart2 {
  320. ralink,group = "uart2";
  321. ralink,function = "uart2";
  322. };
  323. };
  324.  
  325. sdxc_pins: sdxc {
  326. sdxc {
  327. ralink,group = "sdmode";
  328. ralink,function = "sdxc";
  329. };
  330. };
  331.  
  332. pwm0_pins: pwm0 {
  333. pwm0 {
  334. ralink,group = "pwm0";
  335. ralink,function = "pwm0";
  336. };
  337. };
  338.  
  339. pwm1_pins: pwm1 {
  340. pwm1 {
  341. ralink,group = "pwm1";
  342. ralink,function = "pwm1";
  343. };
  344. };
  345.  
  346. pcm_i2s_pins: i2s {
  347. i2s {
  348. ralink,group = "i2s";
  349. ralink,function = "pcm";
  350. };
  351. };
  352. };
  353.  
  354. rstctrl: rstctrl {
  355. compatible = "ralink,mt7620a-reset", "ralink,rt2880-reset";
  356. #reset-cells = <1>;
  357. };
  358.  
  359. clkctrl: clkctrl {
  360. compatible = "ralink,rt2880-clock";
  361. #clock-cells = <1>;
  362. };
  363.  
  364. usbphy: usbphy@10120000 {
  365. compatible = "ralink,mt7628an-usbphy", "mediatek,mt7620-usbphy";
  366. reg = <0x10120000 0x1000>;
  367. #phy-cells = <1>;
  368.  
  369. resets = <&rstctrl 22 &rstctrl 25>;
  370. reset-names = "host", "device";
  371. clocks = <&clkctrl 22 &clkctrl 25>;
  372. clock-names = "host", "device";
  373. };
  374.  
  375. sdhci: sdhci@10130000 {
  376. compatible = "ralink,mt7620-sdhci";
  377. reg = <0x10130000 0x4000>;
  378.  
  379. interrupt-parent = <&intc>;
  380. interrupts = <14>;
  381.  
  382. pinctrl-names = "default";
  383. pinctrl-0 = <&sdxc_pins>;
  384.  
  385. status = "disabled";
  386. };
  387.  
  388. ehci: ehci@101c0000 {
  389. compatible = "generic-ehci";
  390. reg = <0x101c0000 0x1000>;
  391.  
  392. phys = <&usbphy 1>;
  393. phy-names = "usb";
  394.  
  395. interrupt-parent = <&intc>;
  396. interrupts = <18>;
  397. };
  398.  
  399. ohci: ohci@101c1000 {
  400. compatible = "generic-ohci";
  401. reg = <0x101c1000 0x1000>;
  402.  
  403. phys = <&usbphy 1>;
  404. phy-names = "usb";
  405.  
  406. interrupt-parent = <&intc>;
  407. interrupts = <18>;
  408. };
  409.  
  410. ethernet: ethernet@10100000 {
  411. compatible = "ralink,rt5350-eth";
  412. reg = <0x10100000 0x10000>;
  413.  
  414. interrupt-parent = <&cpuintc>;
  415. interrupts = <5>;
  416.  
  417. resets = <&rstctrl 21 &rstctrl 23>;
  418. reset-names = "fe", "esw";
  419.  
  420. mediatek,switch = <&esw>;
  421. };
  422.  
  423. esw: esw@10110000 {
  424. compatible = "mediatek,mt7628-esw", "ralink,rt3050-esw";
  425. reg = <0x10110000 0x8000>;
  426.  
  427. resets = <&rstctrl 23>;
  428. reset-names = "esw";
  429.  
  430. interrupt-parent = <&intc>;
  431. interrupts = <17>;
  432. };
  433.  
  434. pcie: pcie@10140000 {
  435. compatible = "mediatek,mt7620-pci";
  436. reg = <0x10140000 0x100
  437. 0x10142000 0x100>;
  438.  
  439. #address-cells = <3>;
  440. #size-cells = <2>;
  441.  
  442. interrupt-parent = <&cpuintc>;
  443. interrupts = <4>;
  444.  
  445. resets = <&rstctrl 26 &rstctrl 27>;
  446. reset-names = "pcie0", "pcie1";
  447. clocks = <&clkctrl 26 &clkctrl 27>;
  448. clock-names = "pcie0", "pcie1";
  449.  
  450. status = "disabled";
  451.  
  452. device_type = "pci";
  453.  
  454. bus-range = <0 255>;
  455. ranges = <
  456. 0x02000000 0 0x00000000 0x20000000 0 0x10000000 /* pci memory */
  457. 0x01000000 0 0x00000000 0x10160000 0 0x00010000 /* io space */
  458. >;
  459.  
  460. pcie-bridge {
  461. reg = <0x0000 0 0 0 0>;
  462.  
  463. #address-cells = <3>;
  464. #size-cells = <2>;
  465.  
  466. device_type = "pci";
  467. };
  468. };
  469.  
  470. wmac: wmac@10300000 {
  471. compatible = "mediatek,mt7628-wmac";
  472. reg = <0x10300000 0x100000>;
  473.  
  474. interrupt-parent = <&cpuintc>;
  475. interrupts = <6>;
  476.  
  477. status = "disabled";
  478.  
  479. mediatek,mtd-eeprom = <&factory 0x0000>;
  480. mediatek,5ghz = <0>;
  481. };
  482. };
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