module yMux1(z, a, b, c_in);
output z;
input a, b, c_in;
wire not_c, x_and1, y_and2;

not my_not(not_c, c_in);
and my_and1(x_and1, not_c, a);
and my_and2(y_and2, c_in, b);
or my_or(z, x_and1, y_and2);

endmodule