module test(
	in wire clk,

	in wire read_strobe,

	out reg [3:0] addr,
	out reg read_enable,
	in wire [7:0] data
);

localparam IDLE = 1'd 0;
localparam READ = 1'd 1;

reg state;

reg [31:0] buffer;
reg [1:0] read_counter;

always @(posedge clk) begin
	addr <= 4'b 0;
	read_counter <= 2'b 0;

	case (state)
	IDLE: begin
		if (!read_strobe)
			state <= READ;
	end

	READ: begin
		buffer <= {buffer[31:8], data};
		read_counter <= read_counter + 2'b 1;
		if (&read_counter)
			state <= IDLE;
	end
	endcase
end

always @(*) begin
	read_enable = 1'b 0;

	case (state)
	IDLE: begin
	end

	READ: begin
		read_enable = 1'b 1;
	end
	endcase
end

endmodule