----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date:    14:33:36 07/21/2017
-- Design Name:
-- Module Name:    svet - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity svet is
	Port( clk : in  STD_LOGIC;
			led_0 : out  std_logic;
			led_1 : out  std_logic;
			led_2 : out  std_logic;
			led_3 : out  std_logic);
	end svet;

architecture Behavioral of svet is

	signal pulse_pass, flag, pol: std_logic;
	signal led_cnt: integer range 0 to 3 := 0;
	signal clk_div: std_logic_vector(15 downto 0);
	signal duty_cycle: std_logic_vector(9 downto 0);

component pwm is
	generic( max_val: integer := 1000;
				val_bits: integer := 10);
	port( clk: in std_logic;
			val_cur: in std_logic_vector((val_bits -1) downto 0);
			pulse: out std_logic);
end component;

begin



--led_0 <= pulse_pass;

clockDivider: process(clk) -- Clock Divide
begin
	if(clk'event and clk = '1') then
		if (clk_div < 1_999) then
			clk_div <= clk_div + 1;
			flag <= '0';
		else
			clk_div <= (others => '0');
			flag <= '1';

		end if;
	end if;
end process;

dutyCycle:  process(clk) -- Duty Cycle
begin
	if(clk'event and clk = '1') then
		if (flag = '1') then -- 1ms Pulse
			if (pol = '0') then -- Polarity
				if (duty_cycle < 999) then
					duty_cycle <= duty_cycle + 1;
					pol <= '0';

				else
					pol <= '1';
				end if;
			else
				if (duty_cycle = 799) then
						if (led_cnt = 3) then
							led_cnt <= 0;
						end if;
						led_cnt <= led_cnt + 1;

				elsif (duty_cycle > 1) then
					duty_cycle <= duty_cycle - 1;
					pol <= '1';


				else
					pol <= '0';
				end if;
			end if;
		end if;
	end if;
end process;

ccase: process(led_cnt)
begin
	case led_cnt is
		when 0 => led_0 <= pulse_pass;
		when 1 => led_1 <= pulse_pass;
		when 2 => led_2 <= pulse_pass;
		when 3 => led_3 <= pulse_pass;
	end case;
end process;


--button: process(btn_0)
--begin
--	if btn_0 = '1' then
--
--		i <= i + 1;
--		case i is
--		when 0 => led_1 <= pulse_pass;
--			when 1 => led_2 <= pulse_pass;
--				end case;
--	end if;
----	for i in 0 to 1
----	loop
----
----	end loop;
--end process;

pwm0: pwm
generic map(
	max_val => 1000,
	val_bits => 10
	)
port map(
	clk => clk,
	val_cur => duty_cycle,
	pulse => pulse_pass
	);

end Behavioral;