*** SPICE deck for cell lab1{sch} from library elec451
*** Created on Wed Jan 29, 2020 15:13:13
*** Last revised on Wed Jan 29, 2020 15:51:09
*** Written on Wed Jan 29, 2020 15:51:23 by Electric VLSI Design System, version 9.07
*** Layout tech: mocmos, foundry MOSIS
*** UC SPICE *** , MIN_RESIST 4.0, MIN_CAPAC 0.1FF

.global gnd vdd

*** TOP LEVEL CELL: lab1{sch}
Mnmos@0 f a gnd gnd NMOS L=0.6U W=3U
Mnmos@1 f b net@10 gnd NMOS L=0.6U W=3U
Mnmos@2 net@10 c gnd gnd NMOS L=0.6U W=3U
Mpmos@0 vdd a net@29 vdd PMOS L=0.6U W=6U
Mpmos@1 net@29 b f vdd PMOS L=0.6U W=6U
Mpmos@2 net@29 c f vdd PMOS L=0.6U W=6U

* Spice Code nodes in cell cell 'lab1{sch}'
.include C5_models.txt
Vdd vdd gnd 5
Vina c gnd PULSE 0 5 1n 0.1n 0.1n 0.4n 1n
Vinb b gnd PULSE 0 5 2n 0.1n 0.1n 0.8n 2n
Vinc a gnd PULSE 0 5 4n 0.1n 0.1n 1.6n 4n
.tran 10n
.END