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  1. /*
  2. *
  3. * JAGUAR.H Hardware Equates for JAGUAR System
  4. *
  5. * COPYRIGHT 1992-1994 Atari Computer Corporation
  6. * UNAUTHORIZED REPRODUCTION, ADAPTATION, DISTRIBUTION,
  7. * PERFORMANCE OR DISPLAY OF THIS COMPUTER PROGRAM OR
  8. * THE ASSOCIATED AUDIOVISUAL WORK IS STRICTLY PROHIBITED.
  9. * ALL RIGHTS RESERVED.
  10. *
  11. * Revision History:
  12. * 9/19/94 - Consolidated several files into first master JAGUAR.INC (SDS)
  13. * 2/16/95 - MF
  14. * 4/24/95 - Added UART Error Control and Mask definitions (NBK)
  15. * 5/16/95 - Added Asynchronous Serial/DAC Synonyms (SDS)
  16. */
  17.  
  18. /* GENERIC DEFINES */
  19.  
  20. #define DRAM 0x000000L /* Physical Start of RAM */
  21. #define USERRAM 0x004000L /* Start of Available RAM */
  22. #define ENDRAM 0x200000L /* End of RAM */
  23. #define INITSTACK (ENDRAM-4L) /* Recommended Stack Location */
  24.  
  25. /*
  26. * CPU REGISTERS
  27. */
  28.  
  29. #define LEVEL0 0x100L /* 68000 Level 0 Autovector */
  30. #define USER0 0x100L /* Pseudonym */
  31.  
  32. /*
  33. * Masks for INT1 CPU Interrupt Control
  34. */
  35.  
  36. #define C_VIDENA 0x0001L /* Enable CPU Video Interrupts */
  37. #define C_GPUENA 0x0002L /* Enable CPU GPU Interrupts */
  38. #define C_OPENA 0x0004L /* Enable CPU OP Interrupts */
  39. #define C_PITENA 0x0008L /* Enable CPU PIT Interrupts */
  40. #define C_JERENA 0x0010L /* Enable CPU Jerry Interrupts */
  41.  
  42. #define C_VIDCLR 0x0100L /* Clear CPU Video Interrupts */
  43. #define C_GPUCLR 0x0200L /* Clear CPU GPU Interrupts */
  44. #define C_OPCLR 0x0400L /* Clear CPU OP Interrupts */
  45. #define C_PITCLR 0x0800L /* Clear CPU PIT Interrupts */
  46. #define C_JERCLR 0x1000L /* Clear CPU Jerry Interrupts */
  47.  
  48. /*
  49. * JAGUAR REGISTERS
  50. */
  51.  
  52. #define BASE 0xF00000L /* TOM Internal Register Base */
  53.  
  54. /*
  55. * TOM REGISTERS
  56. */
  57.  
  58. #define HC ((volatile short *)(BASE+4)) /* Horizontal Count */
  59. #define VC ((volatile short *)(BASE+6)) /* Vertical Count */
  60. #define LPH ((volatile short *)(BASE+8)) /* Horizontal Lightpen */
  61. #define LPV ((volatile short *)(BASE+0x0A)) /* Vertical Lightpen */
  62. #define OB0 ((volatile short *)(BASE+0x10)) /* Current Object Phrase */
  63. #define OB1 ((volatile short *)(BASE+0x12))
  64. #define OB2 ((volatile short *)(BASE+0x14))
  65. #define OB3 ((volatile short *)(BASE+0x16))
  66. #define OLP ((volatile long *)(BASE+0x20)) /* Object List Pointer */
  67. #define OBF ((volatile short *)(BASE+0x26)) /* Object Processor Flag */
  68. #define VMODE ((volatile short *)(BASE+0x28)) /* Video Mode */
  69. #define BORD1 ((volatile short *)(BASE+0x2A)) /* Border Color (Red & Green) */
  70. #define BORD2 ((volatile short *)(BASE+0x2C)) /* Border Color (Blue) */
  71. #define HDB1 ((volatile short *)(BASE+0x38)) /* Horizontal Display Begin One */
  72. #define HDB2 ((volatile short *)(BASE+0x3A)) /* Horizontal Display Begin Two */
  73. #define HDE ((volatile short *)(BASE+0x3C)) /* Horizontal Display End */
  74. #define VS ((volatile short *)(BASE+0x44)) /* Vertical Sync */
  75. #define VDB ((volatile short *)(BASE+0x46)) /* Vertical Display Begin */
  76. #define VDE ((volatile short *)(BASE+0x48)) /* Vertical Display End */
  77. #define VI ((volatile short *)(BASE+0x4E)) /* Vertical Interrupt */
  78. #define PIT0 ((volatile short *)(BASE+0x50)) /* Programmable Interrupt Timer (Lo) */
  79. #define PIT1 ((volatile short *)(BASE+0x52)) /* Programmable Interrupt Timer (Hi) */
  80. #define BG ((volatile short *)(BASE+0x58)) /* Background Color */
  81.  
  82. #define INT1 ((volatile short *)(BASE+0xE0)) /* CPU Interrupt Control Register */
  83. #define INT2 ((volatile short *)(BASE+0xE2)) /* CPU Interrupt Resume Register */
  84.  
  85. #define CLUT ((volatile short *)(BASE+0x400)) /* Color Lookup Table */
  86.  
  87. #define LBUFA ((volatile long *)(BASE+0x800)) /* Line Buffer A */
  88. #define LBUFB ((volatile long *)(BASE+0x1000)) /* Line Buffer B */
  89. #define LBUFC ((volatile long *)(BASE+0x1800)) /* Line Buffer Current */
  90.  
  91. /*
  92. * OBJECT PROCESSOR EQUATES
  93. */
  94.  
  95. #define BITOBJ 0 /* Bitmap Object Type */
  96. #define SCBITOBJ 1 /* Scaled Bitmap Object Type */
  97. #define GPUOBJ 2 /* GPU Interrupt Object Type */
  98. #define BRANCHOBJ 3 /* Branch Object Type */
  99. #define STOPOBJ 4 /* Stop Object Type */
  100.  
  101. #define O_REFLECT 0x00002000L /* OR with top LONG of BITMAP object */
  102. #define O_RMW 0x00004000L
  103. #define O_TRANS 0x00008000L
  104. #define O_RELEASE 0x00010000L
  105.  
  106. #define O_DEPTH1 (0L<<12) /* DEPTH Field for BITMAP objects */
  107. #define O_DEPTH2 (1L<<12)
  108. #define O_DEPTH4 (2L<<12)
  109. #define O_DEPTH8 (3L<<12)
  110. #define O_DEPTH16 (4L<<12)
  111. #define O_DEPTH32 (5L<<12)
  112.  
  113. #define O_NOGAP (1L<<15) /* Phrase GAP between image phrases */
  114. #define O_1GAP (2L<<15)
  115. #define O_2GAP (3L<<15)
  116. #define O_3GAP (4L<<15)
  117. #define O_4GAP (5L<<15)
  118. #define O_5GAP (6L<<15)
  119. #define O_6GAP (7L<<15)
  120.  
  121. #define O_BREQ (0L<<14) /* CC field of BRANCH objects */
  122. #define O_BRGT (1L<<14)
  123. #define O_BRLT (2L<<14)
  124. #define O_BROP (3L<<14)
  125. #define O_BRHALF (4L<<14)
  126.  
  127. #define O_STOPINTS 0x00000008L /* Enable Interrupts in STOP object */
  128.  
  129. /*
  130. * VIDEO INITIALIZATION CONSTANTS
  131. */
  132.  
  133. #define NTSC_WIDTH 1409 /* Width of screen in clocks */
  134. #define NTSC_HMID 823 /* Middle of screen in clocks */
  135. #define NTSC_HEIGHT 241 /* Height of screen in pixels */
  136. #define NTSC_VMID 266 /* Middle of screen in half-lines */
  137.  
  138. #define PAL_WIDTH 1381 /* Same as above for PAL */
  139. #define PAL_HMID 843
  140. #define PAL_HEIGHT 287
  141. #define PAL_VMID 322
  142.  
  143. /* The following mask will extract the PAL/NTSC flag bit from the */
  144. /* CONFIG register. NTSC = Bit Set, PAL = Bit Clear */
  145.  
  146. #define VIDTYPE 0x10
  147.  
  148. /* The following are Video Mode Register Masks */
  149.  
  150. #define VIDEN 0x0001 /* Enable Video Interrupts */
  151.  
  152. #define CRY16 0x0000 /* 16-bit CRY mode */
  153. #define RGB24 0x0002 /* 24-bit RGB mode */
  154. #define DIRECT16 0x0004 /* 16-bit Direct mode */
  155. #define RGB16 0x0006 /* 16-bit RGB mode */
  156.  
  157. #define GENLOCK 0x0008 /* Not supported on Jaguar Console */
  158. #define INCEN 0x0010 /* Enable Encrustation */
  159. #define BINC 0x0020 /* Select Local Border Color */
  160. #define CSYNC 0x0040 /* Enable Composite Sync */
  161. #define BGEN 0x0080 /* Clear Line Buffer to BG register */
  162. #define VARMOD 0x0100 /* Enable Variable Resolution mode */
  163.  
  164. #define PWIDTH1 0x0000 /* Pixel Dividers */
  165. #define PWIDTH2 0x0200
  166. #define PWIDTH3 0x0400
  167. #define PWIDTH4 0x0600
  168. #define PWIDTH5 0x0800
  169. #define PWIDTH6 0x0A00
  170. #define PWIDTH7 0x0C00
  171. #define PWIDTH8 0x0E00
  172.  
  173. /*
  174. * GPU REGISTERS
  175. */
  176.  
  177. #define G_FLAGS ((volatile long *)(BASE+0x2100)) /* GPU Flags */
  178. #define G_MTXC ((volatile long *)(BASE+0x2104)) /* GPU Matrix Control */
  179. #define G_MTXA ((volatile long *)(BASE+0x2108)) /* GPU Matrix Address */
  180. #define G_END ((volatile long *)(BASE+0x210C)) /* GPU Data Organization */
  181. #define G_PC ((volatile long *)(BASE+0x2110)) /* GPU Program Counter */
  182. #define G_CTRL ((volatile long *)(BASE+0x2114)) /* GPU Operation Control/Status */
  183. #define G_HIDATA ((volatile long *)(BASE+0x2118)) /* GPU Bus Interface high data */
  184. #define G_REMAIN ((volatile long *)(BASE+0x211C)) /* GPU Division Remainder */
  185. #define G_DIVCTRL ((volatile long *)(BASE+0x211C)) /* GPU Divider control */
  186. #define G_RAM ((volatile long *)(BASE+0x3000)) /* GPU Internal RAM */
  187. #define G_ENDRAM ((volatile long *)(((volatile char *)G_RAM)+(4*1024)))
  188.  
  189. /* GPU Flags Register Equates */
  190.  
  191. #define G_CPUENA 0x00000010L /* CPU Interrupt enable bits */
  192. #define G_DSPENA 0x00000020L /* DSP Interrupt enable bits */
  193. #define G_PITENA 0x00000040L /* PIT Interrupt enable bits */
  194. #define G_OPENA 0x00000080L /* Object Processor Interrupt enable bits */
  195. #define G_BLITENA 0x00000100L /* Blitter Interrupt enable bits */
  196. #define G_CPUCLR 0x00000200L /* CPU Interrupt clear bits */
  197. #define G_DSPCLR 0x00000400L /* DSP Interrupt clear bits */
  198. #define G_PITCLR 0x00000800L /* PIT Interrupt clear bits */
  199. #define G_OPCLR 0x00001000L /* Object Processor Interrupt clear bits */
  200. #define G_BLITCLR 0x00002000L /* Blitter Interrupt clear bits */
  201.  
  202. /* GPU Control/Status Register */
  203.  
  204. #define GPUGO 0x00000001L /* Start and Stop the GPU */
  205. /*#define GPUINT0 0x00000004L */ /* generate a GPU type 0 interrupt */
  206.  
  207. #define G_CPULAT 0x00000040L /* Interrupt Latches */
  208. #define G_DSPLAT 0x00000080L
  209. #define G_PITLAT 0x00000100L
  210. #define G_OPLAT 0x00000200L
  211. #define G_BLITLAT 0x00000400L
  212.  
  213. /*
  214. * BLITTER REGISTERS
  215. */
  216.  
  217. #define A1_BASE ((volatile long *)(BASE+0x2200)) /* A1 Base Address */
  218. #define A1_FLAGS ((volatile long *)(BASE+0x2204)) /* A1 Control Flags */
  219. #define A1_CLIP ((volatile long *)(BASE+0x2208)) /* A1 Clipping Size */
  220. #define A1_PIXEL ((volatile long *)(BASE+0x220C)) /* A1 Pixel Pointer */
  221. #define A1_STEP ((volatile long *)(BASE+0x2210)) /* A1 Step (Integer Part) */
  222. #define A1_FSTEP ((volatile long *)(BASE+0x2214)) /* A1 Step (Fractional Part) */
  223. #define A1_FPIXEL ((volatile long *)(BASE+0x2218)) /* A1 Pixel Pointer (Fractional) */
  224. #define A1_INC ((volatile long *)(BASE+0x221C)) /* A1 Increment (Integer Part) */
  225. #define A1_FINC ((volatile long *)(BASE+0x2220)) /* A1 Increment (Fractional Part) */
  226. #define A2_BASE ((volatile long *)(BASE+0x2224)) /* A2 Base Address */
  227. #define A2_FLAGS ((volatile long *)(BASE+0x2228)) /* A2 Control Flags */
  228. #define A2_MASK ((volatile long *)(BASE+0x222C)) /* A2 Address Mask */
  229. #define A2_PIXEL ((volatile long *)(BASE+0x2230)) /* A2 PIXEL */
  230. #define A2_STEP ((volatile long *)(BASE+0x2234)) /* A2 Step (Integer) */
  231.  
  232. #define B_CMD ((volatile long *)(BASE+0x2238)) /* Command */
  233. #define B_COUNT ((volatile long *)(BASE+0x223C)) /* Counters */
  234. #define B_SRCD ((volatile long *)(BASE+0x2240)) /* Source Data */
  235. #define B_DSTD ((volatile long *)(BASE+0x2248)) /* Destination Data */
  236. #define B_DSTZ ((volatile long *)(BASE+0x2250)) /* Destination Z */
  237. #define B_SRCZ1 ((volatile long *)(BASE+0x2258)) /* Source Z (Integer) */
  238. #define B_SRCZ2 ((volatile long *)(BASE+0x2260)) /* Source Z (Fractional) */
  239. #define B_PATD ((volatile long *)(BASE+0x2268)) /* Pattern Data */
  240. #define B_IINC ((volatile long *)(BASE+0x2270)) /* Intensity Increment */
  241. #define B_ZINC ((volatile long *)(BASE+0x2274)) /* Z Increment */
  242. #define B_STOP ((volatile long *)(BASE+0x2278)) /* Collision stop control */
  243.  
  244. #define B_I3 ((volatile long *)(BASE+0x227C)) /* Blitter Intensity 3 */
  245. #define B_I2 ((volatile long *)(BASE+0x2280)) /* Blitter Intensity 2 */
  246. #define B_I1 ((volatile long *)(BASE+0x2284)) /* Blitter Intensity 1 */
  247. #define B_I0 ((volatile long *)(BASE+0x2288)) /* Blitter Intensity 0 */
  248.  
  249. #define B_Z3 ((volatile long *)(BASE+0x228C)) /* Blitter Z 3 */
  250. #define B_Z2 ((volatile long *)(BASE+0x2290)) /* Blitter Z 2 */
  251. #define B_Z1 ((volatile long *)(BASE+0x2294)) /* Blitter Z 1 */
  252. #define B_Z0 ((volatile long *)(BASE+0x2298)) /* Blitter Z 0 */
  253.  
  254. /* BLITTER Command Register defines */
  255.  
  256. #define SRCEN 0x00000001L /* d00: source data read (inner loop) */
  257. #define SRCENZ 0x00000002L /* d01: source Z read (inner loop) */
  258. #define SRCENX 0x00000004L /* d02: source data read (realign) */
  259. #define DSTEN 0x00000008L /* d03: destination data read (inner loop) */
  260. #define DSTENZ 0x00000010L /* d04: destination Z read (inner loop) */
  261. #define DSTWRZ 0x00000020L /* d05: destination Z write (inner loop) */
  262. #define CLIP_A1 0x00000040L /* d06: A1 clipping enable */
  263. #define UPDA1F 0x00000100L /* d08: A1 update step fraction */
  264. #define UPDA1 0x00000200L /* d09: A1 update step */
  265. #define UPDA2 0x00000400L /* d10: A2 update step */
  266. #define DSTA2 0x00000800L /* d11: reverse usage of A1 and A2 */
  267. #define GOURD 0x00001000L /* d12: enable Gouraud shading */
  268. #define ZBUFF 0x00002000L /* d13: polygon Z data updates */
  269. #define TOPBEN 0x00004000L /* d14: intensity carry into byte */
  270. #define TOPNEN 0x00008000L /* d15: intensity carry into nibble */
  271. #define PATDSEL 0x00010000L /* d16: Select pattern data */
  272. #define ADDDSEL 0x00020000L /* d17: diagnostic */
  273. /* d18-d20: Z comparator inhibit */
  274. #define ZMODELT 0x00040000L /* source < destination */
  275. #define ZMODEEQ 0x00080000L /* source = destination */
  276. #define ZMODEGT 0x00100000L /* source > destination */
  277. /* d21-d24: Logic function control */
  278. #define LFU_NAN 0x00200000L /* !source & !destination */
  279. #define LFU_NA 0x00400000L /* !source & destination */
  280. #define LFU_AN 0x00800000L /* source & !destination */
  281. #define LFU_A 0x01000000L /* source & destination */
  282. #define CMPDST 0x02000000L /* d25: pixel compare pattern & dest */
  283. #define BCOMPEN 0x04000000L /* d26: bit compare write inhibit */
  284. #define DCOMPEN 0x08000000L /* d27: data compare write inhibit */
  285. #define BKGWREN 0x10000000L /* d28: data write back */
  286. #define BUSHI 0x20000000L /* d29 blitter priority */
  287. #define SRCSHADE 0x40000000L /* d30: shade src data w/IINC value */
  288.  
  289. /* The following are ALL 16 possible logical operations of the LFUs */
  290.  
  291. #define LFU_ZERO 0x00000000L /* All Zeros */
  292. #define LFU_NSAND 0x00200000L /* NOT Source AND NOT Destination */
  293. #define LFU_NSAD 0x00400000L /* NOT Source AND Destination */
  294. #define LFU_NOTS 0x00600000L /* NOT Source */
  295. #define LFU_SAND 0x00800000L /* Source AND NOT Destination */
  296. #define LFU_NOTD 0x00A00000L /* NOT Destination */
  297. #define LFU_N_SXORD 0x00C00000L /* NOT (Source XOR Destination) */
  298. #define LFU_NSORND 0x00E00000L /* NOT Source OR NOT Destination */
  299. #define LFU_SAD 0x01000000L /* Source AND Destination */
  300. #define LFU_SXORD 0x01200000L /* Source XOR Destination */
  301. #define LFU_D 0x01400000L /* Destination */
  302. #define LFU_NSORD 0x01600000L /* NOT Source OR Destination */
  303. #define LFU_S 0x01800000L /* Source */
  304. #define LFU_SORND 0x01A00000L /* Source OR NOT Destination */
  305. #define LFU_SORD 0x01C00000L /* Source OR Destination */
  306. #define LFU_ONE 0x01E00000L /* All Ones */
  307.  
  308. /* These are some common combinations with less boolean names */
  309.  
  310. #define LFU_REPLACE 0x01800000L /* Source REPLACEs destination */
  311. #define LFU_XOR 0x01200000L /* Source XOR with destination */
  312. #define LFU_CLEAR 0x00000000L /* CLEAR destination */
  313.  
  314. /* BLITTER Flags (A1 or A2) register defines */
  315.  
  316. /* Pitch d00-d01:
  317. distance between pixel phrases */
  318. #define PITCH1 0x00000000L /* 0 phrase gap */
  319. #define PITCH2 0x00000001L /* 1 phrase gap */
  320. #define PITCH4 0x00000002L /* 3 phrase gap */
  321. #define PITCH3 0x00000003L /* 2 phrase gap */
  322.  
  323. /* Pixel d03-d05
  324. bit depth (2^n) */
  325. #define PIXEL1 0x00000000L /* n = 0 */
  326. #define PIXEL2 0x00000008L /* n = 1 */
  327. #define PIXEL4 0x00000010L /* n = 2 */
  328. #define PIXEL8 0x00000018L /* n = 3 */
  329. #define PIXEL16 0x00000020L /* n = 4 */
  330. #define PIXEL32 0x00000028L /* n = 5 */
  331.  
  332. /* Z offset d06-d08
  333. offset from phrase of pixel data from its corresponding
  334. Z data phrases */
  335. #define ZOFFS0 0x00000000L /* offset = 0 UNUSED */
  336. #define ZOFFS1 0x00000040L /* offset = 1 */
  337. #define ZOFFS2 0x00000080L /* offset = 2 */
  338. #define ZOFFS3 0x000000C0L /* offset = 3 */
  339. #define ZOFFS4 0x00000100L /* offset = 4 */
  340. #define ZOFFS5 0x00000140L /* offset = 5 */
  341. #define ZOFFS6 0x00000180L /* offset = 6 */
  342. #define ZOFFS7 0x000001C0L /* offset = 7 UNUSED */
  343.  
  344. /* Width d09-d14
  345. width used for address generation
  346. This is a 6-bit floating point value in pixels
  347. 4-bit unsigned exponent
  348. 2-bit mantissa with implied 3rd bit of 1 */
  349. #define WID2 0x00000800L /* 1.00 X 2^1 ( 4<<9) */
  350. #define WID4 0x00001000L /* 1.00 X 2^2 ( 8<<9) */
  351. #define WID6 0x00001400L /* 1.10 X 2^2 (10<<9) */
  352. #define WID8 0x00001800L /* 1.00 x 2^3 (12<<9) */
  353. #define WID10 0x00001A00L /* 1.01 X 2^3 (13<<9) */
  354. #define WID12 0x00001C00L /* 1.10 X 2^3 (14<<9) */
  355. #define WID14 0x00001E00L /* 1.11 X 2^3 (15<<9) */
  356. #define WID16 0x00002000L /* 1.00 X 2^4 (16<<9) */
  357. #define WID20 0x00002200L /* 1.01 X 2^4 (17<<9) */
  358. #define WID24 0x00002400L /* 1.10 X 2^4 (18<<9) */
  359. #define WID28 0x00002600L /* 1.11 X 2^4 (19<<9) */
  360. #define WID32 0x00002800L /* 1.00 X 2^5 (20<<9) */
  361. #define WID40 0x00002A00L /* 1.01 X 2^5 (21<<9) */
  362. #define WID48 0x00002C00L /* 1.10 X 2^5 (22<<9) */
  363. #define WID56 0x00002E00L /* 1.11 X 2^5 (23<<9) */
  364. #define WID64 0x00003000L /* 1.00 X 2^6 (24<<9) */
  365. #define WID80 0x00003200L /* 1.01 X 2^6 (25<<9) */
  366. #define WID96 0x00003400L /* 1.10 X 2^6 (26<<9) */
  367. #define WID112 0x00003600L /* 1.11 X 2^6 (27<<9) */
  368. #define WID128 0x00003800L /* 1.00 X 2^7 (28<<9) */
  369. #define WID160 0x00003A00L /* 1.01 X 2^7 (29<<9) */
  370. #define WID192 0x00003C00L /* 1.10 X 2^7 (30<<9) */
  371. #define WID224 0x00003E00L /* 1.11 X 2^7 (31<<9) */
  372. #define WID256 0x00004000L /* 1.00 X 2^8 (32<<9) */
  373. #define WID320 0x00004200L /* 1.01 X 2^8 (33<<9) */
  374. #define WID384 0x00004400L /* 1.10 X 2^8 (34<<9) */
  375. #define WID448 0x00004600L /* 1.11 X 2^8 (35<<9) */
  376. #define WID512 0x00004800L /* 1.00 X 2^9 (36<<9) */
  377. #define WID640 0x00004A00L /* 1.01 X 2^9 (37<<9) */
  378. #define WID768 0x00004C00L /* 1.10 X 2^9 (38<<9) */
  379. #define WID896 0x00004E00L /* 1.11 X 2^9 (39<<9) */
  380. #define WID1024 0x00005000L /* 1.00 X 2^10 (40<<9) */
  381. #define WID1280 0x00005200L /* 1.01 X 2^10 (41<<9) */
  382. #define WID1536 0x00005400L /* 1.10 X 2^10 (42<<9) */
  383. #define WID1792 0x00005600L /* 1.11 X 2^10 (43<<9) */
  384. #define WID2048 0x00005800L /* 1.00 X 2^11 (44<<9) */
  385. #define WID2560 0x00005A00L /* 1.01 X 2^11 (45<<9) */
  386. #define WID3072 0x00005C00L /* 1.10 X 2^11 (46<<9) */
  387. #define WID3584 0x00005E00L /* 1.11 X 2^11 (47<<9) */
  388.  
  389. /* X add control d16-d17
  390. controls the update of the X pointer on each pass
  391. round the inner loop */
  392. #define XADDPHR 0x00000000L /* 00 - add phrase width and truncate */
  393. #define XADDPIX 0x00010000L /* 01 - add pixel size (add 1) */
  394. #define XADD0 0x00020000L /* 10 - add zero */
  395. #define XADDINC 0x00030000L /* 11 - add the increment */
  396.  
  397. /* Y add control d18
  398. controls the update of the Y pointer within the inner loop.
  399. it is overridden by the X add control if they are in add increment */
  400. #define YADD0 0x00000000L /* 00 - add zero */
  401. #define YADD1 0x00040000L /* 01 - add 1 */
  402.  
  403. /* X sign d19
  404. add or subtract pixel size if X add control = 01 (XADDPIX) */
  405. #define XSIGNADD 0x00000000L /* 0 - add pixel size */
  406. #define XSIGNSUB 0x00080000L /* 1 - subtract pixel size */
  407.  
  408. /* Y sign d20
  409. add or subtract pixel size if Y add control = 01 (YADD1) */
  410. #define YSIGNADD 0x00000000L /* 0 - add 1 */
  411. #define YSIGNSUB 0x00100000L /* 1 - sub 1 */
  412.  
  413.  
  414. /*
  415. * JERRY REGISTERS
  416. */
  417.  
  418. #define JPIT1 ((volatile short *)(BASE+0x10000L)) /* Timer 1 Pre-Scaler */
  419. #define JPIT2 ((volatile short *)(BASE+0x10002L)) /* Timer 1 Divider */
  420. #define JPIT3 ((volatile short *)(BASE+0x10004L)) /* Timer 2 Pre-Scaler */
  421. #define JPIT4 ((volatile short *)(BASE+0x10006L)) /* Timer 2 Divider */
  422.  
  423. #define J_INT ((volatile short *)(BASE+0x10020L)) /* Jerry Interrupt control (to TOM) */
  424.  
  425. #define JOYSTICK ((volatile short *)(BASE+0x14000L)) /* Joystick register and mute */
  426. #define JOYBUTS ((volatile short *)(BASE+0x14002L)) /* Joystick register */
  427. #define CONFIG ((volatile short *)(BASE+0x14002L)) /* Also has NTSC/PAL */
  428.  
  429. #define SCLK ((volatile long *)(BASE+0x1A150L)) /* SSI Clock Frequency */
  430. #define SMODE ((volatile long *)(BASE+0x1A154L)) /* SSI Control */
  431.  
  432. #define L_I2S ((volatile long *)(BASE+0x1A148L)) /* Left I2S Serial */
  433. #define R_I2S ((volatile long *)(BASE+0x1A14CL)) /* Right I2S Serial */
  434. #define LTXD ((volatile long *)(BASE+0x1A148L)) /* Synonyms */
  435. #define RTXD ((volatile long *)(BASE+0x1A14CL))
  436. #define LRXD ((volatile long *)(BASE+0x1A148L))
  437. #define RRXD ((volatile long *)(BASE+0x1A14CL))
  438.  
  439. #define R_DAC ((volatile long *)(BASE+0x1A148L)) /* Swapped on Purpose! */
  440. #define L_DAC ((volatile long *)(BASE+0x1A14CL))
  441.  
  442. #define ASICLK ((volatile short *)(BASE+0x10034)) /* Async Clock Register */
  443. #define ASICTRL ((volatile short *)(BASE+0x10032)) /* Async Control Register */
  444. #define ASISTAT ((volatile short *)(BASE+0x10032)) /* Async Status Register */
  445. #define ASIDATA ((volatile short *)(BASE+0x10030)) /* Async Data Register */
  446.  
  447. /*
  448. * UART Definitions (new in this file as of 24-Apr-95)
  449. *
  450. * UART control register Masks
  451. * All unused bits in the control register need to be written as zeros !
  452. * With exception of U_CLRERR these are valid for read in ASISTAT, too
  453. */
  454.  
  455. #define U_MODD (1<<0) /* selects odd parity */
  456. #define U_MPAREN (1<<1) /* enable parity */
  457. #define U_MTXOPOL (1<<2) /* transmit output polarity (if set: active low) */
  458. #define U_MRXIPOL (1<<3) /* receive input polarity (if set: invert input) */
  459. #define U_MTINTEN (1<<4) /* enable transmitter interrupts */
  460. #define U_MRINTEN (1<<5) /* enable reciever interrupts */
  461. #define U_MCLRERR (1<<6) /* clear error (only use if U_SERIN is */
  462. /* inactive otherwise the UART locks up. */
  463. /* By default input is active low. This */
  464. /* depends on U_MRXIPOL) */
  465. #define U_MTXBRK (1<<14) /* transmit break */
  466.  
  467. /*
  468. * UART control register (ONLY) bit numbers
  469. */
  470.  
  471. #define U_CLRERR (6)
  472.  
  473. /*
  474. * UART control AND status register (SHARED) bit numbers
  475. */
  476.  
  477. #define U_ODD (0) /* selects odd parity */
  478. #define U_PAREN (1) /* enable parity */
  479. #define U_TXOPOL (2) /* transmit output polarity (if set: active low) */
  480. #define U_RXIPOL (3) /* receive input polarity (if set: invert input) */
  481. #define U_TINTEN (4) /* enable transmitter interrupts */
  482. #define U_RINTEN (5) /* enable reciever interrupts */
  483. #define U_TXBRK (14) /* transmit break */
  484.  
  485. /*
  486. * UART status register (ONLY) bit number
  487. */
  488.  
  489. #define U_ERR (15) /* error condition exists */
  490. #define U_SERIN (13) /* state of UART1 Pin (serial input data) */
  491. #define U_OE (11) /* overrun error */
  492. #define U_FE (10) /* frame error */
  493. #define U_PE (9) /* parity error */
  494. #define U_TBE (8) /* transitter buffer empty */
  495. #define U_RBF (7) /* receiver buffer full */
  496.  
  497.  
  498. /*
  499. * Jerry Interrupt Control Flags
  500. */
  501.  
  502. #define J_EXTENA 0x0001 /* Enable Jerry External Ints */
  503. #define J_DSPENA 0x0002 /* Enable Jerry DSP Ints */
  504. #define J_TIM1ENA 0x0004 /* Enable Jerry Timer 1 Ints */
  505. #define J_TIM2ENA 0x0008 /* Enable Jerry Timer 2 Ints */
  506. #define J_ASYNENA 0x0010 /* Enable Jerry Asynch Serial Ints */
  507. #define J_SYNENA 0x0020 /* Enable Jerry Synch Serial Ints */
  508.  
  509. #define J_EXTCLR 0x0100 /* Clear Pending External Ints */
  510. #define J_DSPCLR 0x0200 /* Clear Pending DSP Ints */
  511. #define J_TIM1CLR 0x0400 /* Clear Pending Timer 1 Ints */
  512. #define J_TIM2CLR 0x0800 /* Clear Pending Timer 2 Ints */
  513. #define J_ASYNCLR 0x1000 /* Clear Pending Asynch Serial Ints */
  514. #define J_SYNCLR 0x2000 /* Clear Pending Synch Serial Ints */
  515.  
  516. /*
  517. * Joystick Equates
  518. *
  519. * Bits when LONGword is formatted as below (from JOYTEST\JT_LOOP.S).
  520. * Format: xxApxxBx RLDU147* xxCxxxox 2580369#
  521. */
  522.  
  523. #define JOY_UP 20 /*joypad */
  524. #define JOY_DOWN 21
  525. #define JOY_LEFT 22
  526. #define JOY_RIGHT 23
  527.  
  528. #define FIRE_A 29 /*fire buttons */
  529. #define FIRE_B 25
  530. #define FIRE_C 13
  531. #define OPTION 9
  532. #define PAUSE 28
  533.  
  534. #define KEY_STAR 16 /*keypad */
  535. #define KEY_7 17
  536. #define KEY_4 18
  537. #define KEY_1 19
  538.  
  539. #define KEY_0 4
  540. #define KEY_8 5
  541. #define KEY_5 6
  542. #define KEY_2 7
  543.  
  544. #define KEY_HASH 0
  545. #define KEY_9 1
  546. #define KEY_6 2
  547. #define KEY_3 3
  548.  
  549. #define ANY_JOY 0x00F00000L /* AND joyedge with this - joypad was pressed if result is not 0 */
  550. #define ANY_FIRE 0x32002200L /* AND joyedge with this - A,B C, Option or Pause was pressed if result is not 0 */
  551. #define ANY_KEY 0x000F00FFL /* AND joyedge with this - 123456789*0# was pressed if result is not 0 */
  552.  
  553. /*
  554. * ROM Tables built into Jerry - 128 samples each
  555. * 16 bit samples sign extended to 32
  556. */
  557.  
  558. #define ROM_TABLE ((volatile long *)(BASE+0x1D000L)) /* Base of tables */
  559.  
  560. #define ROM_TRI ((volatile long *)(BASE+0x1D000L)) /* A triangle wave */
  561. #define ROM_SINE ((volatile long *)(BASE+0x1D200L)) /* Full amplitude SINE */
  562. #define ROM_AMSINE ((volatile long *)(BASE+0x1D400L)) /* Linear (?) ramp SINE */
  563. #define ROM_12W ((volatile long *)(BASE+0x1D600L)) /* SINE(X)+SINE(2*X) : (was ROM_SINE12W) */
  564. #define ROM_CHIRP16 ((volatile long *)(BASE+0x1D800L)) /* SHORT SWEEP */
  565. #define ROM_NTRI ((volatile long *)(BASE+0x1DA00L)) /* Triangle w/NOISE */
  566. #define ROM_DELTA ((volatile long *)(BASE+0x1DC00L)) /* Positive spike */
  567. #define ROM_NOISE ((volatile long *)(BASE+0x1DE00L)) /* Noise */
  568.  
  569. /*
  570. * JERRY Registers (DSP)
  571. */
  572.  
  573. #define D_FLAGS ((volatile long *)(BASE+0x1A100L)) /* DSP Flags */
  574. #define D_MTXC ((volatile long *)(BASE+0x1A104L)) /* DSP Matrix Control */
  575. #define D_MTXA ((volatile long *)(BASE+0x1A108L)) /* DSP Matrix Address */
  576. #define D_END ((volatile long *)(BASE+0x1A10CL)) /* DSP Data Organization */
  577. #define D_PC ((volatile long *)(BASE+0x1A110L)) /* DSP Program Counter */
  578. #define D_CTRL ((volatile long *)(BASE+0x1A114L)) /* DSP Operation Control/Status */
  579. #define D_MOD ((volatile long *)(BASE+0x1A118L)) /* DSP Modulo Instruction Mask */
  580. #define D_REMAIN ((volatile long *)(BASE+0x1A11CL)) /* DSP Division Remainder */
  581. #define D_DIVCTRL ((volatile long *)(BASE+0x1A11CL)) /* DSP Divider control */
  582. #define D_MACHI ((volatile long *)(BASE+0x1A120L)) /* DSP Hi byte of MAC operations */
  583. #define D_RAM ((volatile long *)(BASE+0x1B000L)) /* DSP Internal RAM */
  584. #define D_ENDRAM ((volatile long *)(((volatile char *)D_RAM)+(8*1024)))
  585.  
  586. /*
  587. * JERRY Flag Register Equates
  588. */
  589.  
  590. #define D_CPUENA 0x00000010L /* CPU Interrupt Enable Bit */
  591. #define D_I2SENA 0x00000020L /* I2S Interrupt Enable Bit */
  592. #define D_TIM1ENA 0x00000040L /* Timer 1 Interrupt Enable Bit */
  593. #define D_TIM2ENA 0x00000080L /* Timer 2 Interrupt Enable Bit */
  594. #define D_EXT0ENA 0x00000100L /* External Interrupt 0 Enable Bit */
  595. #define D_EXT1ENA 0x00010000L /* External Interrupt 1 Enable Bit */
  596.  
  597. #define D_CPUCLR 0x00000200L /* CPU Interrupt Clear Bit */
  598. #define D_I2SCLR 0x00000400L /* I2S Interrupt Clear Bit */
  599. #define D_TIM1CLR 0x00000800L /* Timer 1 Interrupt Clear Bit */
  600. #define D_TIM2CLR 0x00001000L /* Timer 2 Interrupt Clear Bit */
  601. #define D_EXT0CLR 0x00002000L /* External Interrupt 0 Clear Bit */
  602. #define D_EXT1CLR 0x00020000L /* External Interrupt 1 Clear Bit */
  603.  
  604. /*
  605. * JERRY Control/Status Register
  606. */
  607.  
  608. #define DSPGO 0x00000001L /* Start DSP */
  609. #define DSPINT0 0x00000004L /* Generate a DSP Interrupt 0 */
  610.  
  611. #define D_CPULAT 0x00000040L /* Interrupt Latches */
  612. #define D_I2SLAT 0x00000080L
  613. #define D_TIM1LAT 0x00000100L
  614. #define D_TIM2LAT 0x00000200L
  615. #define D_EXT1LAT 0x00000400L
  616. #define D_EXT2LAT 0x00010000L
  617.  
  618. /*
  619. * JERRY Modulo Instruction Masks
  620. */
  621.  
  622. #define MODMASK2 0xFFFFFFFEL /* 2 byte circular buffer */
  623. #define MODMASK4 0xFFFFFFFCL /* 4 byte circular buffer */
  624. #define MODMASK8 0xFFFFFFF8L /* 8 byte circular buffer */
  625. #define MODMASK16 0xFFFFFFF0L /* 16 byte circular buffer */
  626. #define MODMASK32 0xFFFFFFE0L /* 32 byte circular buffer */
  627. #define MODMASK64 0xFFFFFFC0L /* 64 byte circular buffer */
  628. #define MODMASK128 0xFFFFFF80L /* 128 byte circular buffer */
  629. #define MODMASK256 0xFFFFFF00L /* 256 byte circular buffer */
  630. #define MODMASK512 0xFFFFFE00L /* 512 byte circular buffer */
  631. #define MODMASK1K 0xFFFFFC00L /* 1k circular buffer */
  632. #define MODMASK2K 0xFFFFF800L /* 2k circular buffer */
  633. #define MODMASK4K 0xFFFFF000L /* 4k circular buffer */
  634. #define MODMASK8K 0xFFFFE000L /* 8k circular buffer */
  635. #define MODMASK16K 0xFFFFC000L /* 16k circular buffer */
  636. #define MODMASK32K 0xFFFF8000L /* 32k circular buffer */
  637. #define MODMASK64K 0xFFFF0000L /* 64k circular buffer */
  638. #define MODMASK128K 0xFFFE0000L /* 128k circular buffer */
  639. #define MODMASK256K 0xFFFC0000L /* 256k circular buffer */
  640. #define MODMASK512K 0xFFF80000L /* 512k circular buffer */
  641. #define MODMASK1M 0xFFF00000L /* 1M circular buffer */
  642.  
  643. /*
  644. * SHARED Equates for TOM (GPU) and JERRY (DSP)
  645. */
  646.  
  647. /* Control/Status Registers */
  648.  
  649. #define RISCGO 0x00000001L /* Start GPU or DSP */
  650. #define CPUINT 0x00000002L /* Allow the GPU/DSP to interrupt CPU */
  651. #define FORCEINT0 0x00000004L /* Cause an INT 0 on GPU or DSP */
  652. #define SINGLE_STEP 0x00000008L /* Enter SINGLE_STEP mode */
  653. #define SINGLE_GO 0x00000010L /* Execute one instruction */
  654.  
  655. #define REGPAGE 0x00004000L /* Register Bank Select */
  656. #define DMAEN 0x00008000L /* Enable DMA LOAD and STORE */
  657.  
  658. /* Flags Register */
  659.  
  660. #define ZERO_FLAG 0x00000001L /* ALU Zero Flag */
  661. #define CARRY_FLAG 0x00000002L /* ALU Carry Flag */
  662. #define NEGA_FLAG 0x00000004L /* ALU Negative Flag */
  663.  
  664. #define IMASK 0x00000008L /* Interrupt Service Mask */
  665.  
  666. /* Matrix Control Register */
  667.  
  668. #define MATRIX3 0x00000003L /* use for 3x1 Matrix */
  669. #define MATRIX4 0x00000004L /* etc... */
  670. #define MATRIX5 0x00000005L
  671. #define MATRIX6 0x00000006L
  672. #define MATRIX7 0x00000007L
  673. #define MATRIX8 0x00000008L
  674. #define MATRIX9 0x00000009L
  675. #define MATRIX10 0x0000000AL
  676. #define MATRIX11 0x0000000BL
  677. #define MATRIX12 0x0000000CL
  678. #define MATRIX13 0x0000000DL
  679. #define MATRIX14 0x0000000EL
  680. #define MATRIX15 0x0000000FL
  681.  
  682. #define MATROW 0x00000000L /* Access Matrix by Row */
  683. #define MATCOL 0x00000010L /* Access Matrix by Column */
  684.  
  685. /* Data Organisation Register */
  686.  
  687. #define BIG_IO 0x00010001L /* Make I/O Big-Endian */
  688. #define BIG_PIX 0x00020002L /* Access Pixels in Big-Endian */
  689. #define BIG_INST 0x00040004L /* Fetch Instructions in Big-Endian */
  690.  
  691. /* Divide Unit Control */
  692.  
  693. #define DIV_OFFSET 0x00000001L /* Divide 16.16 values if set */
  694.  
  695.  
  696.  
  697. /**********************************************************************/
  698. /* Old definitions maintained for compatibility with old source code. */
  699. /* You must #define _COMPAT_ (1) for these to be active. */
  700. /**********************************************************************/
  701.  
  702. #if (_COMPAT_ == 1)
  703.  
  704. #define MOD_MASK ((volatile long *)(BASE+0x1A118L)) /* Mask for ADDQ(SUBQ)MOD */
  705.  
  706. #endif
  707.  
  708. /*******/
  709. /* EOF */
  710. /*******/
  711.  
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