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  1. 2006/09/01 Revision 1.2
  2. -----------------------------------------------------------------
  3.  
  4.  
  5. This is a description of the VMX128-type opcodes found on
  6. the xbox360 processor. I figured this out by looking at
  7. various disassmblies, so there might some errors and
  8. missing instructions. Some instructions have unknown
  9. semantics for me.
  10.  
  11. See comments or corrections to sb#biallas.net
  12.  
  13.  
  14. =================================================================
  15. Conventions:
  16. VD128, VS128: 5 lower bits of a VMX128 vector register
  17. number
  18. VDh: upper 2 bits of VD128
  19. (so register number is (VDh << 5 | VD128))
  20.  
  21. VA128: same as VD128
  22. A: bit 6 of VA128
  23. a: bit 5 of VA128
  24. (so register number is (A<<6 | a<<5 | VA128))
  25.  
  26. VB128: same as VD128
  27. VBh: same as VDh
  28.  
  29. VC128: 3 bits of a VMX128 vector register number
  30. (you can only use vr0-vr7 here)
  31.  
  32. RA, RB: general purpose register number
  33.  
  34. UIMM: unsigned immediate value
  35. SIMM: signed immediate value
  36.  
  37. PERMh: upper 3 bits of a permutation
  38. PERMl: lower 5 bits of a permutation
  39.  
  40. x, y, z: unknown immediate values
  41.  
  42. =================================================================
  43. lvewx128 Load Vector128 Element Word Indexed
  44. |0 0 0 1 0 0| VD128 | RA | RB |0 0 0 1 0 0 0|VDh|1 1|
  45.  
  46. lvewx128 vr(VD128), r(RA), r(RB)
  47.  
  48.  
  49. =================================================================
  50. lvlx128 Load Vector128 Left Indexed
  51. |0 0 0 1 0 0| VD128 | RA | RB |1 0 0 0 0 0 0|VDh|1 1|
  52.  
  53. lvlx128 vr(VD128), r(RA), r(RB)
  54.  
  55.  
  56. =================================================================
  57. lvrx128 Load Vector128 Right Indexed
  58. |0 0 0 1 0 0| VD128 | RA | RB |1 0 0 0 1 0 0|VDh|1 1|
  59.  
  60. lvrx128 vr(VD128), r(RA), r(RB)
  61.  
  62.  
  63. =================================================================
  64. lvlxl128 Load Vector128 Left Indexed LRU
  65. |0 0 0 1 0 0| VD128 | RA | RB |1 1 0 0 0 0 0|VDh|1 1|
  66.  
  67. lvlxl128 vr(VD128), r(RA), r(RB)
  68.  
  69.  
  70. =================================================================
  71. lvrxl128 Load Vector128 Right Indexed LRU
  72. |0 0 0 1 0 0| VD128 | RA | RB |1 1 0 0 1 0 0|VDh|1 1|
  73.  
  74. lvrxl128 vr(VD128), r(RA), r(RB)
  75.  
  76.  
  77. =================================================================
  78. lvsl128 Load Vector128 for Shift Left
  79. |0 0 0 1 0 0| VD128 | RA | RB |0 0 0 0 0 0 0|VDh|1 1|
  80.  
  81. lvsl128 vr(VD128), r(RA), r(RB)
  82.  
  83.  
  84. =================================================================
  85. lvsr128 Load Vector128 for Shift Right
  86. |0 0 0 1 0 0| VD128 | RA | RB |0 0 0 0 1 0 0|VDh|1 1|
  87.  
  88. lvsr128 vr(VD128), r(RA), r(RB)
  89.  
  90.  
  91. =================================================================
  92. lvx128 Load Vector128 Indexed
  93. |0 0 0 1 0 0| VD128 | RA | RB |0 0 0 1 1 0 0|VDh|1 1|
  94.  
  95. lvx128 vr(VD128), r(RA), r(RB)
  96.  
  97.  
  98. =================================================================
  99. lvxl128 Load Vector128 Indexed LRU
  100. |0 0 0 1 0 0| VD128 | RA | RB |0 1 0 1 1 0 0|VDh|1 1|
  101.  
  102. lvxl128 vr(VD128), r(RA), r(RB)
  103.  
  104.  
  105. =================================================================
  106. stewx128 Store Vector128 Element Word Indexed
  107. |0 0 0 1 0 0| VS128 | RA | RB |0 1 1 0 0 0 0|VDh|1 1|
  108.  
  109. stvewx128 vr(VS128), r(RA), r(RB)
  110.  
  111.  
  112. =================================================================
  113. stvlx128 Store Vector128 Left Indexed
  114. |0 0 0 1 0 0| VS128 | RA | RB |1 0 1 0 0 0 0|VDh|1 1|
  115.  
  116. stvlx128 vr(VS128), r(RA), r(RB)
  117.  
  118.  
  119. =================================================================
  120. stvlxl128 Store Vector128 Left Indexed LRU
  121. |0 0 0 1 0 0| VS128 | RA | RB |1 1 1 0 0 0 0|VDh|1 1|
  122.  
  123. lvlxl128 vr(VS128), r(RA), r(RB)
  124.  
  125.  
  126. =================================================================
  127. stvrx128 Store Vector128 Right Indexed
  128. |0 0 0 1 0 0| VS128 | RA | RB |1 0 1 0 1 0 0|VDh|1 1|
  129.  
  130. stvrx128 vr(VS128), r(RA), r(RB)
  131.  
  132.  
  133. =================================================================
  134. stvrxl128 Store Vector128 Right Indexed LRU
  135. |0 0 0 1 0 0| VS128 | RA | RB |1 1 1 0 1 0 0|VDh|1 1|
  136.  
  137. stvrxl128 vr(VS128), r(RA), r(RB)
  138.  
  139.  
  140. =================================================================
  141. stvx128 Store Vector128 Indexed
  142. |0 0 0 1 0 0| VS128 | RA | RB |0 0 1 1 1 0 0|VDh|1 1|
  143.  
  144. stvx128 vr(VS128), r(RA), r(RB)
  145.  
  146.  
  147. =================================================================
  148. stvxl128 Store Vector128 Indexed LRU
  149. |0 0 0 1 0 0| VS128 | RA | RB |0 1 1 1 1 0 0|VDh|1 1|
  150.  
  151. stvxl128 vr(VS128), r(RA), r(RB)
  152.  
  153.  
  154. =================================================================
  155. vaddfp128 Vector128 Add Floating Point
  156. |0 0 0 1 0 1| VD128 | VA128 | VB128 |A|0 0 0 0|a|1|VDh|VBh|
  157.  
  158. vaddfp128 vr(VD128), vr(VA128), vr(VB128)
  159.  
  160.  
  161. =================================================================
  162. vand128 Vector128 Logical AND
  163. |0 0 0 1 0 1| VD128 | VA128 | VB128 |A|1 0 0 0|a|1|VDh|VBh|
  164.  
  165. vand128 vr(VD128), vr(VA128), vr(VB128)
  166.  
  167.  
  168. =================================================================
  169. vandc128 Vector128 Logical AND
  170. with Complement
  171. |0 0 0 1 0 1| VD128 | VA128 | VB128 |A|1 0 1 0|a|1|VDh|VBh|
  172.  
  173. vandc128 vr(VD128), vr(VA128), vr(VB128)
  174.  
  175.  
  176. =================================================================
  177. vcfpsxws128 Vector128 Convert From Floating-Point to
  178. Signed Fixed-Point Word Saturate
  179. |0 0 0 1 1 0| VD128 | SIMM | VB128 |0 1 0 0 0 1 1|VDh|VBh|
  180.  
  181. vcfpsxws128 vr(VD128), vr(VB128), SIMM
  182.  
  183.  
  184. =================================================================
  185. vcfpuxws128 Vector128 Convert From Floating-Point to
  186. Unsigned Fixed-Point Word Saturate
  187. |0 0 0 1 1 0| VD128 | UIMM | VB128 |0 1 0 0 1 1 1|VDh|VBh|
  188.  
  189. vcfpuxws128 vr(VD128), vr(VB128), UIMM
  190.  
  191.  
  192. =================================================================
  193. vcmpbfp128 Vector128 Compare Bounds
  194. Floating Point
  195. |0 0 0 1 1 0| VD128 | VA128 | VB128 |A|0 1 1|R|a|0|VDh|VBh|
  196.  
  197. vcmpbfp128 vr(VD128), vr(VA128), vr(VB128) (R == 0)
  198. vcmpbfp128. vr(VD128), vr(VA128), vr(VB128) (R == 1)
  199.  
  200.  
  201. =================================================================
  202. vcmpeqfp128 Vector128 Compare Equal-to
  203. Floating Point
  204. |0 0 0 1 1 0| VD128 | VA128 | VB128 |A|0 0 0|R|a|0|VDh|VBh|
  205.  
  206. vcmpeqfp128 vr(VD128), vr(VA128), vr(VB128) (R == 0)
  207. vcmpeqfp128. vr(VD128), vr(VA128), vr(VB128) (R == 1)
  208.  
  209.  
  210. =================================================================
  211. vcmpequw128 Vector128 Compare Equal-to
  212. Unsigned Word
  213. |0 0 0 1 1 0| VD128 | VA128 | VB128 |A|1 0 0|R|a|0|VDh|VBh|
  214.  
  215. vcmpequw128 vr(VD128), vr(VA128), vr(VB128) (R == 0)
  216. vcmpequw128. vr(VD128), vr(VA128), vr(VB128) (R == 1)
  217.  
  218.  
  219. =================================================================
  220. vcmpgefp128 Vector128 Compare Greater-Than-
  221. or-Equal-to Floating Point
  222. |0 0 0 1 1 0| VD128 | VA128 | VB128 |A|0 0 1|R|a|0|VDh|VBh|
  223.  
  224. vcmpgefp128 vr(VD128), vr(VA128), vr(VB128) (R == 0)
  225. vcmpgefp128. vr(VD128), vr(VA128), vr(VB128) (R == 1)
  226.  
  227.  
  228. =================================================================
  229. vcmpgtfp128 Vector128 Compare Greater-Than
  230. Floating-Point
  231. |0 0 0 1 1 0| VD128 | VA128 | VB128 |A|0 1 0|R|a|0|VDh|VBh|
  232.  
  233. vcmpgtfp128 vr(VD128), vr(VA128), vr(VB128) (R == 0)
  234. vcmpgtfp128. vr(VD128), vr(VA128), vr(VB128) (R == 1)
  235.  
  236.  
  237. =================================================================
  238. vcsxwfp128 Vector128 Convert From Signed Fixed-Point
  239. Word to Floating-Point
  240. |0 0 0 1 1 0| VD128 | UIMM | VB128 |0 1 0 1 0 1 1|VDh|VBh|
  241.  
  242. vcsxwfp128 vr(VD128), vr(VB128), SIMM
  243.  
  244.  
  245. =================================================================
  246. vcuxwfp128 Vector128 Convert From Unsigned Fixed-Point
  247. Word to Floating-Point
  248. |0 0 0 1 1 0| VD128 | UIMM | VB128 |0 1 0 1 1 1 1|VDh|VBh|
  249.  
  250. vcuxwfp128 vr(VD128), vr(VB128), UIMM
  251.  
  252.  
  253. =================================================================
  254. vexptefp128 Vector128 2 Raised to the Exponent
  255. Estimate Floating Point
  256. |0 0 0 1 1 0| VD128 |0 0 0 0 0| VB128 |1 1 0 1 0 1 1|VDh|VBh|
  257.  
  258. vexptefp128 vr(VD128), vr(VB128)
  259.  
  260.  
  261. =================================================================
  262. vlogefp128 Vector128 Log2 Estimate
  263. Floating Point
  264. |0 0 0 1 1 0| VD128 |0 0 0 0 0| VB128 |1 1 0 1 1 1 1|VDh|VBh|
  265.  
  266. vlogefp128 vr(VD128), vr(VB128)
  267.  
  268.  
  269. =================================================================
  270. vmaddcfp128 Vector128 Multiply Add
  271. Floating Point
  272. |0 0 0 1 0 1| VDS128 | VA128 | VB128 |A|0 1 0 0|a|1|VDh|VBh|
  273.  
  274. vmaddcfp128 vr(VDS128), vr(VA128), vr(VSD128), vr(VB128)
  275.  
  276.  
  277. =================================================================
  278. vmaddfp128 Vector128 Multiply Add
  279. Floating Point
  280. |0 0 0 1 0 1| VDS128 | VA128 | VB128 |A|0 0 1 1|a|1|VDh|VBh|
  281.  
  282. vmaddfp128 vr(VDS128), vr(VA128), vr(VB128), vr(VDS128)
  283.  
  284.  
  285. =================================================================
  286. vmaxfp128 Vector128 Maximum
  287. Floating Point
  288. |0 0 0 1 1 0| VD128 | VA128 | VB128 |A|1 0 1 0|a|0|VDh|VBh|
  289.  
  290. vmaxfp128 vr(VD128), vr(VA128), vr(VB128)
  291.  
  292.  
  293. =================================================================
  294. vminfp128 Vector128 Minimum
  295. Floating Point
  296. |0 0 0 1 1 0| VD128 | VA128 | VB128 |A|1 0 1 1|a|0|VDh|VBh|
  297.  
  298. vminfp128 vr(VD128), vr(VA128), vr(VB128)
  299.  
  300.  
  301. =================================================================
  302. vmrghw128 Vector128 Merge High Word
  303. |0 0 0 1 1 0| VD128 | VA128 | VB128 |A|1 1 0 0|a|0|VDh|VBh|
  304.  
  305. vmrghw128 vr(VD128), vr(VA128), vr(VB128)
  306.  
  307.  
  308. =================================================================
  309. vmrglw128 Vector128 Merge Low Word
  310. |0 0 0 1 1 0| VD128 | VA128 | VB128 |A|1 1 0 1|a|0|VDh|VBh|
  311.  
  312. vmrglw128 vr(VD128), vr(VA128), vr(VB128)
  313.  
  314.  
  315. =================================================================
  316. vmsum3fp128 Vector128 Multiply Sum 3-way
  317. Floating Point
  318. |0 0 0 1 0 1| VD128 | VA128 | VB128 |A|0 1 1 0|a|1|VDh|VBh|
  319.  
  320. vmsub3fp128 vr(VD128), vr(VA128), vr(VB128)
  321.  
  322.  
  323. =================================================================
  324. vmsum4fp128 Vector128 Multiply Sum 4-way
  325. Floating-Point
  326. |0 0 0 1 0 1| VD128 | VA128 | VB128 |A|0 1 1 1|a|1|VDh|VBh|
  327.  
  328. vmsub4fp128 vr(VD128), vr(VA128), vr(VB128)
  329.  
  330.  
  331. =================================================================
  332. vmulfp128 Vector128 Multiply
  333. Floating-Point
  334. |0 0 0 1 0 1| VD128 | VA128 | VB128 |A|0 0 1 0|a|1|VDh|VBh|
  335.  
  336. vmulfp128 vr(VD128), vr(VA128), vr(VB128)
  337.  
  338.  
  339. =================================================================
  340. vnmsubfp128 Vector128 Negative Multiply-Subtract
  341. Floating Point
  342. |0 0 0 1 0 1| VDS128 | VA128 | VB128 |A|0 1 0 1|a|1|VDh|VBh|
  343.  
  344. vnmsubfp128 vr(VDS128), vr(VA128), vr(VB128), vr(VDS128)
  345.  
  346.  
  347. =================================================================
  348. vnor128 Vector128 Logical NOR
  349. |0 0 0 1 0 1| VD128 | VA128 | VB128 |A|1 0 1 0|a|1|VDh|VBh|
  350.  
  351. vnor128 vr(VD128), vr(VA128), vr(VB128)
  352.  
  353.  
  354. =================================================================
  355. vor128 Vector128 Logical OR
  356. |0 0 0 1 0 1| VD128 | VA128 | VB128 |A|1 0 1 1|a|1|VDh|VBh|
  357.  
  358. vor128 vr(VD128), vr(VA128), vr(VB128)
  359.  
  360.  
  361. =================================================================
  362. vperm128 Vector128 Permutation
  363. |0 0 0 1 0 1| VD128 | VA128 | VB128 |A|0| VC |a|0|VDh|VBh|
  364.  
  365. vperm128 vr(VD128), vr(VA128), vr(VB128), vr(VC)
  366.  
  367.  
  368. =================================================================
  369. vpermwi128 Vector128 Permutate Word Immediate
  370. |0 0 0 1 1 0| VD128 | PERMl | VB128 |0|1|PERMh|0|1|VDh|VBh|
  371.  
  372. vpermwi128 vr(VD128), vr(VB128), (PERMh << 5 | PERMl)
  373.  
  374.  
  375. =================================================================
  376. vpkd3d128 Vector128 Pack D3Dtype, Rotate Left
  377. Immediate and Mask Insert
  378. |0 0 0 1 1 0| VD128 | x | y | VB128 |1 1 0| z |0 1|VDh|VBh|
  379.  
  380. vpkd3d128 vr(VD128), vr(VB128), x, y, z
  381.  
  382.  
  383. =================================================================
  384. vpkshss128 Vector128 Pack Signed Half Word
  385. Signed Saturate
  386. |0 0 0 1 0 1| VD128 | VA128 | VB128 |A|1 0 0 0|a|0|VDh|VBh|
  387.  
  388. vpkshss128 vr(VD128), vr(VA128), vr(VB128)
  389.  
  390.  
  391. =================================================================
  392. vpkshus128 Vector128 Pack Signed Half Word
  393. Unsigned Saturate
  394. |0 0 0 1 0 1| VD128 | VA128 | VB128 |A|1 0 0 1|a|0|VDh|VBh|
  395.  
  396. vpkshus128 vr(VD128), vr(VA128), vr(VB128)
  397.  
  398.  
  399. =================================================================
  400. vpkswss128 Vector128 Pack Signed Word
  401. Signed Saturate
  402. |0 0 0 1 0 1| VD128 | VA128 | VB128 |A|1 0 1 0|a|0|VDh|VBh|
  403.  
  404. vpkswss128 vr(VD128), vr(VA128), vr(VB128)
  405.  
  406.  
  407. =================================================================
  408. vpkswus128 Vector128 Pack Signed Word
  409. Unsigned Saturate
  410. |0 0 0 1 0 1| VD128 | VA128 | VB128 |A|1 0 1 1|a|0|VDh|VBh|
  411.  
  412. vpkswus128 vr(VD128), vr(VA128), vr(VB128)
  413.  
  414.  
  415. =================================================================
  416. vpkuhum128 Vector128 Pack Unsigned Half Word
  417. Unsigned Modulo
  418. |0 0 0 1 0 1| VD128 | VA128 | VB128 |A|1 1 0 0|a|0|VDh|VBh|
  419.  
  420. vpkuhum128 vr(VD128), vr(VA128), vr(VB128)
  421.  
  422.  
  423. =================================================================
  424. vpkuhus128 Vector128 Pack Unsigned Half Word
  425. Unsigned Saturate
  426. |0 0 0 1 0 1| VD128 | VA128 | VB128 |A|1 1 0 1|a|0|VDh|VBh|
  427.  
  428. vpkuhus128 vr(VD128), vr(VA128), vr(VB128)
  429.  
  430.  
  431. =================================================================
  432. vpkuwum128 Vector128 Pack Unsigned Word
  433. Unsigned Modulo
  434. |0 0 0 1 0 1| VD128 | VA128 | VB128 |A|1 1 1 0|a|0|VDh|VBh|
  435.  
  436. vpkuwum128 vr(VD128), vr(VA128), vr(VB128)
  437.  
  438.  
  439. =================================================================
  440. vpkuwus128 Vector128 Pack Unsigned Word
  441. Unsigned Saturate
  442. |0 0 0 1 0 1| VD128 | VA128 | VB128 |A|1 1 1 1|a|0|VDh|VBh|
  443.  
  444. vpkuwus128 vr(VD128), vr(VA128), vr(VB128)
  445.  
  446.  
  447. =================================================================
  448. vrefp128 Vector128 Reciprocal Estimate
  449. Floating Point
  450. |0 0 0 1 1 0| VD128 |0 0 0 0 0| VB128 |1 1 0 0 0 1 1|VDh|VBh|
  451.  
  452. vrefp128 vr(VD128), vr(VB128)
  453.  
  454.  
  455. =================================================================
  456. vrfim128 Vector128 Round to Floating-Point
  457. Integer toward -oo
  458. |0 0 0 1 1 0| VD128 |0 0 0 0 0| VB128 |0 1 1 0 0 1 1|VDh|VBh|
  459.  
  460. vrfim128 vr(VD128), vr(VB128)
  461.  
  462.  
  463. =================================================================
  464. vrfin128 Vector128 Round to Floating-Point
  465. Integer toward Nearest
  466. |0 0 0 1 1 0| VD128 |0 0 0 0 0| VB128 |0 1 1 0 1 1 1|VDh|VBh|
  467.  
  468. vrfin128 vr(VD128), vr(VB128)
  469.  
  470.  
  471. =================================================================
  472. vrfip128 Vector128 Round to Floating-Point
  473. Integer toward +oo
  474. |0 0 0 1 1 0| VD128 |0 0 0 0 0| VB128 |0 1 1 1 0 1 1|VDh|VBh|
  475.  
  476. vrfip128 vr(VD128), vr(VB128)
  477.  
  478.  
  479. =================================================================
  480. vrfiz128 Vector128 Round to Floating-Point
  481. Integer toward Zero
  482. |0 0 0 1 1 0| VD128 |0 0 0 0 0| VB128 |0 1 1 1 1 1 1|VDh|VBh|
  483.  
  484. vrfiz128 vr(VD128), vr(VB128)
  485.  
  486.  
  487. =================================================================
  488. vrlimi128 Vector128 Rotate Left Immediate
  489. and Mask Insert
  490. |0 0 0 1 1 0| VD128 | UIMM | VB128 |1 1 1| z |0 1|VDh|VBh|
  491.  
  492. vrlimi128 vr(VD128), vr(VB128), UIMM, z
  493.  
  494.  
  495. =================================================================
  496. vrlw128 Vector128 Rotate Left Word
  497. |0 0 0 1 0 1| VD128 | VA128 | VB128 |A|0 0 0 1|a|1|VDh|VBh|
  498.  
  499. vrlw128 vr(VD128), vr(VA128), vr(VB128)
  500.  
  501.  
  502. =================================================================
  503. vrsqrtefp128 Vector128 Reciprocal Square Root
  504. Estimate Floating Point
  505. |0 0 0 1 1 0| VD128 |0 0 0 0 0| VB128 |1 1 0 0 1 1 1|VDh|VBh|
  506.  
  507. vrsqrtefp128 vr(VD128), vr(VB128)
  508.  
  509.  
  510. =================================================================
  511. vsel128 Vector128 Select
  512. |0 0 0 1 0 1| VDS128 | VA128 | VB128 |A|1 1 0 1|a|1|VDh|VBh|
  513.  
  514. vsel128 vr(VDS128), vr(VA128), vr(VB128), vr(VDS128)
  515.  
  516.  
  517. =================================================================
  518. vsldoi128 Vector128 Shift Left Double
  519. by Octet Immediate
  520. |0 0 0 1 0 0| VD128 | VA128 | VB128 |A| SHB |a|1|VDh|VBh|
  521.  
  522. vsldoi128 vr(VD128), vr(VA128), vr(VB128), SHB
  523.  
  524.  
  525. =================================================================
  526. vslo128 Vector128 Shift Left Octet
  527. |0 0 0 1 0 1| VD128 | VA128 | VB128 |A|1 1 1 0|a|1|VDh|VBh|
  528.  
  529. vslo128 vr(VD128), vr(VA128), vr(VB128)
  530.  
  531.  
  532. =================================================================
  533. vslw128 Vector128 Shift Left Word
  534. |0 0 0 1 1 0| VD128 | VA128 | VB128 |A|0 0 1 1|a|1|VDh|VBh|
  535.  
  536. vslw128 vr(VD128), vr(VA128), vr(VB128)
  537.  
  538.  
  539. =================================================================
  540. vspltisw128 Vector128 Splat Immediate
  541. Signed Word
  542. |0 0 0 1 1 0| VD128 | SIMM | VB128 |1 1 1 0 1 1 1|VDh|VBh|
  543.  
  544. vspltisw128 vr(VD128), vr(VB128), SIMM
  545.  
  546.  
  547. =================================================================
  548. vspltw128 Vector128 Splat Word
  549. |0 0 0 1 1 0| VD128 | UIMM | VB128 |1 1 1 0 0 1 1|VDh|VBh|
  550.  
  551. vspltw128 vr(VD128), vr(VB128), UIMM
  552.  
  553.  
  554. =================================================================
  555. vsraw128 Vector128 Shift Right
  556. Arithmetic Word
  557. |0 0 0 1 1 0| VD128 | VA128 | VB128 |A|0 1 0 1|a|1|VDh|VBh|
  558.  
  559. vsraw128 vr(VD128), vr(VA128), vr(VB128)
  560.  
  561.  
  562. =================================================================
  563. vsro128 Vector128 Shift Right Octet
  564. |0 0 0 1 1 0| VD128 | VA128 | VB128 |A|1 1 1 1|a|1|VDh|VBh|
  565.  
  566. vsro128 vr(VD128), vr(VA128), vr(VB128)
  567.  
  568.  
  569. =================================================================
  570. vsrw128 Vector128 Shift Right Word
  571. |0 0 0 1 1 0| VD128 | VA128 | VB128 |A|0 1 1 1|a|1|VDh|VBh|
  572.  
  573. vsrw128 vr(VD128), vr(VA128), vr(VB128)
  574.  
  575.  
  576. =================================================================
  577. vsubfp128 Vector128 Subtract Floating Point
  578. |0 0 0 1 0 1| VD128 | VA128 | VB128 |A|0 0 0 1|a|1|VDh|VBh|
  579.  
  580. vsubfp128 vr(VD128), vr(VA128), vr(VB128)
  581.  
  582.  
  583. =================================================================
  584. vupkd3d128 Vector128 Unpack D3Dtype
  585. |0 0 0 1 1 0| VD128 | UIMM | VB128 |1 1 1 1 1 1 1|VDh|VBh|
  586.  
  587. vupkd3d128 vr(VD128), vr(VB128), UIMM
  588.  
  589.  
  590. =================================================================
  591. vupkhsb128 Vector128 Unpack
  592. High Signed Byte
  593. |0 0 0 1 1 0| VD128 |0 0 0 0 0| VB128 |0 1 1 1 0 0 0|VDh|VBh|
  594.  
  595. vupkhsb128 vr(VD128), vr(VB128)
  596.  
  597.  
  598. =================================================================
  599. vupklsb128 Vector128 Unpack
  600. Low Signed Byte
  601. |0 0 0 1 1 0| VD128 |0 0 0 0 0| VB128 |0 1 1 1 1 0 0|VDh|VBh|
  602.  
  603. vupkhsb128 vr(VD128), vr(VB128)
  604.  
  605.  
  606. =================================================================
  607. vxor128 Vector128 Logical XOR
  608. |0 0 0 1 0 1| VD128 | VA128 | VB128 |A|1 1 0 0|a|1|VDh|VBh|
  609.  
  610. vxor128 vr(VD128), vr(VA128), vr(VB128)
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