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RCA Map

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Feb 18th, 2017
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  1. Release 14.5 Map P.58f (nt64)
  2. Xilinx Mapping Report File for Design 'RCAdd_Sub'
  3.  
  4. Design Information
  5. ------------------
  6. Command Line : map -intstyle ise -p xc3s250e-tq144-4 -cm area -ir off -pr off
  7. -c 100 -o RCAdd_Sub_map.ncd RCAdd_Sub.ngd RCAdd_Sub.pcf
  8. Target Device : xc3s250e
  9. Target Package : tq144
  10. Target Speed : -4
  11. Mapper Version : spartan3e -- $Revision: 1.55 $
  12. Mapped Date : Sat Feb 18 11:42:41 2017
  13.  
  14. Design Summary
  15. --------------
  16. Number of errors: 0
  17. Number of warnings: 0
  18. Logic Utilization:
  19. Number of 4 input LUTs: 17 out of 4,896 1%
  20. Logic Distribution:
  21. Number of occupied Slices: 9 out of 2,448 1%
  22. Number of Slices containing only related logic: 9 out of 9 100%
  23. Number of Slices containing unrelated logic: 0 out of 9 0%
  24. *See NOTES below for an explanation of the effects of unrelated logic.
  25. Total Number of 4 input LUTs: 17 out of 4,896 1%
  26. Number of bonded IOBs: 27 out of 108 25%
  27.  
  28. Average Fanout of Non-Clock Nets: 2.21
  29.  
  30. Peak Memory Usage: 245 MB
  31. Total REAL time to MAP completion: 8 secs
  32. Total CPU time to MAP completion: 1 secs
  33.  
  34. NOTES:
  35.  
  36. Related logic is defined as being logic that shares connectivity - e.g. two
  37. LUTs are "related" if they share common inputs. When assembling slices,
  38. Map gives priority to combine logic that is related. Doing so results in
  39. the best timing performance.
  40.  
  41. Unrelated logic shares no connectivity. Map will only begin packing
  42. unrelated logic into a slice once 99% of the slices are occupied through
  43. related logic packing.
  44.  
  45. Note that once logic distribution reaches the 99% level through related
  46. logic packing, this does not mean the device is completely utilized.
  47. Unrelated logic packing will then begin, continuing until all usable LUTs
  48. and FFs are occupied. Depending on your timing budget, increased levels of
  49. unrelated logic packing may adversely affect the overall timing performance
  50. of your design.
  51.  
  52. Table of Contents
  53. -----------------
  54. Section 1 - Errors
  55. Section 2 - Warnings
  56. Section 3 - Informational
  57. Section 4 - Removed Logic Summary
  58. Section 5 - Removed Logic
  59. Section 6 - IOB Properties
  60. Section 7 - RPMs
  61. Section 8 - Guide Report
  62. Section 9 - Area Group and Partition Summary
  63. Section 10 - Timing Report
  64. Section 11 - Configuration String Information
  65. Section 12 - Control Set Information
  66. Section 13 - Utilization by Hierarchy
  67.  
  68. Section 1 - Errors
  69. ------------------
  70.  
  71. Section 2 - Warnings
  72. --------------------
  73.  
  74. Section 3 - Informational
  75. -------------------------
  76. INFO:MapLib:562 - No environment variables are currently set.
  77. INFO:LIT:244 - All of the single ended outputs in this design are using slew
  78. rate limited output drivers. The delay on speed critical single ended outputs
  79. can be dramatically reduced by designating them as fast outputs.
  80.  
  81. Section 4 - Removed Logic Summary
  82. ---------------------------------
  83.  
  84. Section 5 - Removed Logic
  85. -------------------------
  86.  
  87. Section 6 - IOB Properties
  88. --------------------------
  89.  
  90. +---------------------------------------------------------------------------------------------------------------------------------------------------------+
  91. | IOB Name | Type | Direction | IO Standard | Diff | Drive | Slew | Reg (s) | Resistor | IOB |
  92. | | | | | Term | Strength | Rate | | | Delay |
  93. +---------------------------------------------------------------------------------------------------------------------------------------------------------+
  94. | a<0> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 |
  95. | a<1> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 |
  96. | a<2> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 |
  97. | a<3> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 |
  98. | a<4> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 |
  99. | a<5> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 |
  100. | a<6> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 |
  101. | a<7> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 |
  102. | b<0> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 |
  103. | b<1> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 |
  104. | b<2> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 |
  105. | b<3> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 |
  106. | b<4> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 |
  107. | b<5> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 |
  108. | b<6> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 |
  109. | b<7> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 |
  110. | carry_out | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
  111. | overflow | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
  112. | subtract | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 |
  113. | sum<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
  114. | sum<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
  115. | sum<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
  116. | sum<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
  117. | sum<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
  118. | sum<5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
  119. | sum<6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
  120. | sum<7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
  121. +---------------------------------------------------------------------------------------------------------------------------------------------------------+
  122.  
  123. Section 7 - RPMs
  124. ----------------
  125.  
  126. Section 8 - Guide Report
  127. ------------------------
  128. Guide not run on this design.
  129.  
  130. Section 9 - Area Group and Partition Summary
  131. --------------------------------------------
  132.  
  133. Partition Implementation Status
  134. -------------------------------
  135.  
  136. No Partitions were found in this design.
  137.  
  138. -------------------------------
  139.  
  140. Area Group Information
  141. ----------------------
  142.  
  143. No area groups were found in this design.
  144.  
  145. ----------------------
  146.  
  147. Section 10 - Timing Report
  148. --------------------------
  149. This design was not run using timing mode.
  150.  
  151. Section 11 - Configuration String Details
  152. -----------------------------------------
  153. Use the "-detail" map option to print out Configuration Strings
  154.  
  155. Section 12 - Control Set Information
  156. ------------------------------------
  157. No control set information for this architecture.
  158.  
  159. Section 13 - Utilization by Hierarchy
  160. -------------------------------------
  161. Use the "-detail" map option to print out the Utilization by Hierarchy section.
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