module my_ram32x4(
    input [4:0] Address,
    input clk,
    input [3:0] DataIn,
    input Write,
    output [3:0] DataOut);

    reg [3:0] memory_array[31:0];

    reg [4:0] reg_Address;
    reg [3:0] reg_DataIn;
    reg reg_Write;

    always @(posedge clk)
    begin
        reg_Address <= Address;
        reg_DataIn <= DataIn;
        reg_Write <= Write;
    end

    always @(*)
        if (reg_Write) memory_array[reg_Address] = reg_DataIn;

    assign DataOut = memory_array[reg_Address];
endmodule