module fifo_arbiter(
    input A,
    input B,
    input C,
    input D,
    input CLK,
    output reg [3:0] fifo_take,
    output reg [1:0] ADDR,
    output reg READY
);

reg [3:0] states;

initial begin
    states = 0;
    fifo_take <= 0;
end

always @(posedge CLK)
begin
        if(A || B || C || D)
        begin
        READY <= 1;
            if(A && ~ states[0])
            begin
                ADDR <= 0;
                states[0] <= 1;
                fifo_take <= {0,0,0,1};
            end
            else
            begin
                if(B && ~states[1])
                begin
                    ADDR <= 1;
                    states[1] <= 1;
                    fifo_take <= {0,0,1,0};
                end
                else
                begin
                    if(C && ~states[2])
                    begin
                        ADDR <= 2;
                        states[2] <= 1;
                        fifo_take <= {0,1,0,0};
                    end
                    else
                    begin
                        if(D && ~states[3])
                        begin
                            ADDR <= 3;
                            states[3] <= 1;
                            fifo_take <= {1,0,0,0};
                        end
                        else
                            fifo_take <= {0,0,0,0};
                    end
                end
            end

        if(states == {D, C, B, A} || states == fifo_take)
            states <= 0;

        end
        else
        begin
            READY <= 0;
            states <= 0;
            fifo_take <= {0,0,0,0};
        end
end

endmodule