RenHao

new_9x11

Mar 29th, 2015
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  1. module LCD_CTRL(clk, reset, datain, cmd, cmd_valid, dataout, output_valid, busy);
  2.  
  3. input clk;
  4. input reset;
  5. input [7:0] datain;
  6. input [2:0] cmd;
  7. input cmd_valid;
  8.  
  9. output reg [7:0] dataout;
  10. output reg output_valid;
  11. output reg busy;
  12.  
  13. endmodule
  14. -----------------------------------------------------------------------------------------
  15. module Decoder(cmd_in,cmdv_in,,reset,clk,ld_en,cmd_out);
  16.  
  17. input [2:0]cmd_in;
  18. input cmdv_in,clk,reset;
  19.  
  20. output reg ld_en;
  21. output reg [2:0]cmd_out;
  22.  
  23. always@(posedge clk or posedge reset)
  24. begin
  25. if(reset)
  26. begin
  27.     ld_en <= 0;
  28.     cmd_out <= 0;
  29. end
  30.  
  31. else if(cmdv_in)
  32. begin
  33.     cmd_out <= cmd_in;
  34.     if(cmd_in == 3'b000)
  35.         ld_en <= 1;
  36. end
  37.  
  38. end
  39.  
  40.  
  41.  
  42. endmodule
  43. -----------------------------------------------------------------------------------------
  44. module LoadData(data_in,en,reset,clk,data_out);
  45.  
  46. input [7:0]data_in;
  47. input en,reset,clk;
  48.  
  49. output reg [7:0]data_out;
  50.  
  51. integer i;
  52.  
  53. always@(posedge clk or posedge reset)
  54. begin
  55.     if(reset)
  56.     begin
  57.         data_out <= 0;
  58.     end
  59.  
  60.     else if(en)
  61.     begin
  62.         data_out <= data_in;
  63.     end
  64. end
  65.  
  66. endmodule
  67. -----------------------------------------------------------------------------------------
  68. module ImBuff(data_in,clk,reset,data_out);
  69.  
  70. input [7:0]data_in;
  71. input clk,reset;
  72.  
  73. output reg [7:0]data_out;
  74.  
  75. reg [7:0]temp[107:0];
  76.  
  77. integer i;
  78.  
  79. always@(posedge clk or posedge reset)
  80. begin
  81. if(reset)
  82.     begin
  83.         i <= 0;
  84.     end
  85.  
  86. else
  87.     begin
  88.         if( i == 108 )
  89.         begin
  90.             i <= 0;
  91.         end
  92.        
  93.         else
  94.         begin
  95.             i <= i+1;
  96.         end
  97.     end
  98. end
  99.  
  100. always@(posedge clk or posedge reset)
  101. begin
  102.  
  103.     if(reset)
  104.     begin
  105.         temp[i] <= 0;
  106.     end
  107.  
  108.     else
  109.     begin
  110.         temp[i] <= data_in;
  111.         data_out <= temp[i];
  112.     end
  113.  
  114. end
  115.  
  116. endmodule
  117. -----------------------------------------------------------------------------------------
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