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- library ieee;
- use ieee.std_logic_1164.all;
- use ieee.numeric_std.all;
- use ieee.std_logic_arith.all;
- use ieee.std_logic_textio.all;
- use std.textio.all;
- entity HFA_tb is
- end HFA_tb;
- architecture behave of HFA_tb is
- --clock 100 MHz change to any value suitable
- constant c_CLOCK_PERIOD : time:= 100 ns;
- signal r_CLOCK : std_logic := '0';
- --**signal r_ENABLE : std_logic := '0';
- signal r_adcpulse : integer;
- signal r_hitstart : integer; ---output of single threshold
- signal r_hitend : integer;
- signal r_hitpeak : integer;
- signal r_peaktime : integer;
- signal r_hitsum : integer;
- signal r_opready : std_logic := '0';
- --more signal
- --describe HFA component here (Unit Under Test)
- component HFA is
- port (
- adcpulse_i : in integer;
- clk : in std_logic;
- hitstart_o : out integer; ---output of single threshold
- hitend_o : out integer;
- hitpeak_o : out integer;
- peaktime_o : out integer;
- hitsum_o : out integer;
- opready_o : out std_logic
- );
- end component HFA;
- begin
- --Instatiate the unit under test
- UUT : HFA
- port map (
- clk => r_CLOCK,
- adcpulse_i => r_adcpulse,
- hitstart_o => r_hitstart,
- hitend_o => r_hitend,
- hitpeak_o => r_hitpeak,
- peaktime_o => r_peaktime,
- hitsum_o => r_hitsum,
- opready_o => r_opready
- );
- p_CLK_GEN : process is
- begin
- wait for c_CLOCK_PERIOD/2;
- r_CLOCK <= not r_CLOCK;
- end process p_CLK_GEN;
- --main testing logic for reading from text file; feed in the loop and check output
- process
- file in_buffer : text;
- file out_buffer : text;
- variable v_ILINE : line;
- variable v_OLINE : line;
- variable v_adcValue : integer;
- variable line_counter : integer :=0;
- variable block_length : integer :=0;
- variable block_counter : integer :=0;
- variable header_length : integer :=0;
- type H is array (0 to 2) of integer;
- begin
- file_open(in_buffer,"sample.txt",read_mode);
- file_open(out_buffer,"results.txt",write_mode);
- while not endfile(in_buffer) loop
- if line_counter=0 then
- f1 : for k in 0 to 2 loop
- readline(in_buffer, v_ILINE);
- read(v_ILINE, v_adcValue);
- H(0) := v_adcValue;
- line_counter := line_counter+1;
- end loop f1;
- end if;
- if line_counter /= 2 and block_length /= 9 then
- f2 : for k in 0 to 2 loop
- readline(in_buffer, v_ILINE);
- read(v_ILINE, v_adcValue);
- r_adcpulse <= v_adcValue;
- line_counter := line_counter+1;
- block_length := block_length+1;
- end loop f2;
- end if;
- if block_length=9 then
- f3 : for k in 0 to 2 loop
- readline(in_buffer, v_ILINE);
- read(v_ILINE, v_adcValue);
- header(k) <= v_adcValue;
- line_counter := line_counter+1;
- header_length := header_length+1;
- if header_length=3 then
- block_length := 0;
- exit;
- end if;
- end loop f3;
- end if;
- wait for c_CLOCK_PERIOD;
- end loop;
- if endfile(in_buffer) then
- write(v_OLINE, string'("hit_start_time"));
- writeline(out_buffer, v_OLINE);
- write(v_OLINE, r_hitstart);
- writeline(out_buffer, v_OLINE);
- end if;
- wait for c_CLOCK_PERIOD;
- file_close(in_buffer);
- file_close(out_buffer);
- wait;
- end process;
- MONITOR:
- process
- begin
- if now > 0 ns then
- report "header = " & to_string(header);
- end if;
- end process;
- end behave;
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