Binary Reg/Reg Operations - x64

( This is Forth code to generate instruction stream bytes for the )
( x64 architecture for register-to-register binary operations.    )
(                                                                 )
( The code has been tested along each "axis" - starting with      )
( rax rax add and walking each term through its value sequence.   )
( Items in the bulk of the matrix have only been spot checked.    )

 0 const rax   1 const rcx   2 const rdx   3 const rbx
 4 const rsp   5 const rbp   6 const rsi   7 const rdi
 8 const r8    9 const r9   10 const r10  11 const r11
12 const r12  13 const r13  14 const r14  15 const r15

: bits>  rot and swap >> or ;
: <bits  rot and swap << or ;
: dest  over 16 7 <bits swap 3 8 bits> ;
: src  over 19 7 <bits swap 1 8 bits> ;
: inst,  swap here ! allot ;
: rrop  builds> 11 << x:C00148 or , does> @ src dest 3 inst, ;

0 rrop rradd  1 rrop rror   2 rrop rradc  3 rrop rrsbb
4 rrop rrand  5 rrop rrsub  6 rrop rrxor  7 rrop rrcmp