module test (
    // 48 MHz clock
    input clk,
    input [3:0] sw, // unused

    output ds_dp, ds_g, ds_c, ds_d,
    output ds_a, ds_b, ds_e, ds_f,
    output [3:0] ds_en,

    output [4:0] vga_red,
    output [5:0] vga_green,
    output [4:0] vga_blue,
    output vga_hsync, vga_vsync,

    inout ps2_data, ps2_clk,

    output bell // unused
);

// UNCOMMENTING THIS BREAKS PS/2

/*
// PLL
wire pixel_clk;

pll pll (
    .inclk0(clk),
    .c0(pixel_clk)
);

// VGA (outputs current x, y and active video bit)
wire [9:0] vga_x, vga_y;
wire vga_active;
vga vga (
    .pixel_clk(pixel_clk),
    .x(vga_x),
    .y(vga_y),
    .active(vga_active),
    .hsync(vga_hsync),
    .vsync(vga_vsync)
);

// Grapher (outputs pixel colors)

grapher grapher (
    .pixel_clk(pixel_clk),
    .x(vga_x),
    .y(vga_y),
    .active(vga_active),
    .red(vga_red),
    .green(vga_green),
    .blue(vga_blue)
);
*/

// PS/2

wire [7:0] ps2_cmd_out;
wire ps2_cmd_out_ready;
wire [7:0] ps2_cmd_in;
wire ps2_cmd_in_ready;
wire ps2_busy;

ps2 ps2 (
    .clk(clk),
    .ps2_clk(ps2_clk),
    .ps2_data(ps2_data),
    .cmd_out(ps2_cmd_out),
    .cmd_out_ready(ps2_cmd_out_ready),
    .cmd_in(ps2_cmd_in),
    .cmd_in_ready(ps2_cmd_in_ready),
    .busy(ps2_busy)
);

// PS/2 mouse
/*
wire [7:0] ps2_mouse_x;
wire [7:0] ps2_mouse_y;

ps2_mouse ps2_mouse (
    .clk(clk),
    .cmd_in(ps2_cmd_in),
    .cmd_in_ready(ps2_cmd_in_ready),
    .busy(ps2_busy),
    .cmd_out(ps2_cmd_out),
    .cmd_out_ready(ps2_cmd_out_ready),
    .x(ps2_mouse_x),
    .y(ps2_mouse_y)
);

reg [7:0] mouse_x = 0;
reg [7:0] mouse_y = 0;

always @(posedge clk) begin
    mouse_x <= mouse_x + ps2_mouse_x;
    mouse_y <= mouse_y + ps2_mouse_y;
end
*/

// seg

// displaying current command on 7 seg
wire [15:0] seg_num = ps2_cmd_in; //{mouse_x, mouse_y};

seg seg (
    .clk(clk),
    .num(seg_num),
    .segs({ds_a, ds_b, ds_c, ds_d, ds_e, ds_f, ds_g, ds_dp}),
    .mask(ds_en)
);

endmodule

module ps2 (
    input clk,

    inout ps2_clk,
    inout ps2_data,

    input [7:0] cmd_out,
    input cmd_out_ready, // active for 1 clock cycle

    output reg [7:0] cmd_in,
    output reg cmd_in_ready, // active for 1 clock cycle

    output reg busy // 1 if either sending or receiving
);

initial begin
    busy <= 0;
    cmd_in <= 0;
    cmd_in_ready <= 0;
end

reg ps2_clk_enable = 0;
assign ps2_clk = ps2_clk_enable ? 1'b0 : 1'bZ;

wire ps2_clk_in; // input from ps2_clk, synchronized
sync clk_sync (
    .clk(clk),
    .in(ps2_clk),
    .out(ps2_clk_in)
);

reg ps2_data_enable = 0;
reg ps2_data_out = 0;
assign ps2_data = ps2_data_enable ? ps2_data_out : 1'bZ;

wire ps2_data_in; // input from ps2_data, synchronized
sync data_sync (
    .clk(clk),
    .in(ps2_data),
    .out(ps2_data_in)
);

/*
0 -> inactive, waiting for new input

send to ps2 states
1 -> start inhibit ps2 clock
2 -> inhibit ps2 clock, and release ps2_clk
3 -> send data, parity bit
4 -> send stop bit
5 -> wait for ack bit, goto inactive state 0

receive from ps2 states
6 -> receive data, receive parity
7 -> receive stop
8 -> cmd_in_ready set to high
9 -> cmd_in_ready set to low
*/

reg [3:0] state = 0;

reg [7:0] cmd = 0; // internal buffer for the command to be sent
reg [12:0] counter = 0; // used for inhibit and counting bits for shiftregs
reg cycle = 0; // used for edge detection
reg parity = 0; // parity bit, what else to say

always @(posedge clk) begin
    // state reacting to system clock
    case (state)
        0: if (cmd_out_ready) begin
            cmd <= cmd_out;
            busy <= 1;

            state <= 1;
        end
        1: begin
            ps2_clk_enable <= 1;

            state <= 2;
        end
        2: begin
            counter <= counter + 1'b1;

            if (counter == 5000) begin
                // set counter to count bits
                counter <= 8;
                ps2_clk_enable <= 0;
                ps2_data_out <= 0;
                ps2_data_enable <= 1;

                state <= 3;
            end
        end
        8: begin
            cmd_in_ready <= 1;

            state <= 9;
        end
        9: begin
            cmd_in_ready <= 0;

            state <= 0;
        end
    endcase

    if (!ps2_clk_in) begin
        if (cycle) begin
            cycle <= 0;

            // state reacting to ps2 clock
            case (state)
                // receive check
                0: if (!busy) begin
                    busy <= 1;
                    // counter to count bits
                    counter <= 8;

                    state <= 6;
                end

                // send states
                3: if (counter == 0) begin
                    // parity bit
                    ps2_data_out <= ~parity;
                    parity <= 0;

                    state <= 4;
                end else begin
                    counter <= counter - 1'b1;
                    ps2_data_out <= cmd [0];
                    parity <= parity ^ (cmd [0]);
                    cmd <= cmd >> 1;
                end
                4: begin
                    // stop bit
                    ps2_data_out <= 0;
                    ps2_data_enable <= 0;

                    state <= 5;
                end
                5: if (!ps2_data_in) begin
                    busy <= 0;

                    state <= 0;
                end

                // receive states
                6: if (counter == 0) begin
                    // parity
                    // TODO: parity check
                    parity <= 0;

                    state <= 7;
                end else begin
                    cmd_in <= (cmd_in >> 1) | {ps2_data_in, 7'b0000000};
                    counter <= counter - 1'b1;
                end
                7: begin
                    // stop bit
                    busy <= 0;
                    state <= 8;
                end
            endcase
        end
    end else begin
        cycle <= 1;
    end
end

endmodule

module sync (
    input clk,

    input in,
    output reg out
);

reg r0 = 0;

always @(posedge clk) begin
    r0 <= in;
    out <= r0;
end

endmodule