library ieee;
  use ieee.std_logic_1164.all;
  use ieee.numeric_std.all;
  use ieee.std_logic_unsigned.all;

  entity Boot is
    port(x, y: in std_logic_vector(7 downto 0); o:out std_logic_vector(15 downto 0));
  end Boot;

  architecture boot of Boot is
    begin

      process(x, y)
        variable a: std_logic_vector(16 downto 0);
        variable s,p : std_logic_vector(7 downto 0);
        variable i: integer;

          begin
            a := "00000000000000000";
            s := y;
            a(8 downto 1) := x;

            for i in 0 to 7 loop
              if(a(1) = '1' and a(0) = '0') then
                p := (a(16 downto 9));
                a(16 downto 9) := (p-s);

              elsif(a(1) = '0' and a(0) = '1') then
                p := (a(16 downto 9));
                a(16 downto 9) := (p+s);

              end if;

              a(15 downto 0) := a(16 downto 1);

            end loop;

            o(15 downto 0) <= a(16 downto 1);

          end process;

        end boot;

library ieee;
  use ieee.std_logic_1164.all;
  use ieee.numeric_std.all;
  use ieee.std_logic_unsigned.all;

  entity test_boot is
  end test_boot;

  architecture tba of test_boot is
    component boot
      port(x, y: in std_logic_vector(7 downto 0); o: out std_logic_vector(15 downto 0));
  end component;

  signal x_t, y_t: std_logic_vector(7 downto 0);
  signal o_t: std_logic_vector(15 downto 0);

  begin
    cpn_t:boot port map(x_t, y_t, o_t);
    x_t <= "00110101", "10001101" after 100 us, "10111100" after 200 us;
    y_t <= "01011101", "00011100" after 100 us, "10011111" after 200 us;
  end tba;