miau

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-- Company:
-- Engineer:
--
-- Create Date: 05/04/2019 08:57:33 PM
-- Design Name:
-- Module Name: main - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity main is
       Port (
           SW : in STD_LOGIC_VECTOR (15 downto 0);
           Clk : in STD_LOGIC;
           Rst,BTNM,next_number,equals : in STD_LOGIC;
           An : out STD_LOGIC_VECTOR (7 downto 0);
           Seg : out STD_LOGIC_VECTOR (7 downto 0);
		   JA : inout  STD_LOGIC_VECTOR (7 downto 0)); -- PmodKYPD is designed to be connected to JA
end main;

architecture Behavioral of main is
-- pi+0.2 = 4055c28f ; - 403c28f6
signal n1:std_logic_vector(31 downto 0):=x"4048f5c3";
signal n2:std_logic_vector(31 downto 0):=x"3e4ccccd";
signal sgn1,sgn2, zero,sign:std_logic;
signal sgn_entry_1,sgn_entry_2,OANA1,OANA2:std_logic_vector(0 downto 0);
signal exp1,exp2,exp_max,exp_min,dif,final_exp:std_logic_vector(7 downto 0);
signal radix1, radix2:std_logic_vector(22 downto 0);
signal signs:std_logic_vector(1 downto 0);
signal radix_n1, radix_n2, radix_min, radix_max, radix_shifted, radix_entry_1, radix_entry_2,result,shifted_result:std_logic_vector(23 downto 0);
signal ld:std_logic:='1';
signal op:std_logic:='0';
signal shift_exp : STD_LOGIC_VECTOR (9 downto 0);
signal subnormal1,subnormal2, min,out_of_range:std_logic;
signal final_number : std_logic_vector(31 downto 0);
signal dif_10bits: std_logic_vector(9 downto 0);
signal Decode: STD_LOGIC_VECTOR (3 downto 0);
signal overflow:std_logic;
signal btnm_debounced, next_number_debounced, equals_debounced : std_logic;
signal shift_digit : std_logic;
signal Data, fout: STD_LOGIC_VECTOR(31 downto 0);
signal current_digit, show_result: std_logic := '0';
begin


C0: entity WORK.Decoder port map (clk=>clk, Row =>JA(7 downto 4), Col=>JA(3 downto 0), DecodeOut=> Decode);

deb:entity work.debouncer
    port map (clk,BTNM,
    btnm_debounced
    );
deb2:entity work.debouncer
    port map (clk,next_number,
    next_number_debounced
    );
deb3:entity work.debouncer
    port map (clk,equals,
    equals_debounced
    );

Conv102: entity InFloat port map ( clk, rst,
           btnm_debounced,
           Decode,
           fout);

--process(next_number_debounced, Rst)
--begin
--    if Rst = '1' then
--        current_digit <= '0';
--    elsif next_number_debounced = '1' then
--        if current_digit = '0' then
--            n1 <= fout;
--        else
--            n2 <= fout;
--        end if;
--        current_digit <= not current_digit;
--    end if;
--end process;

process(sw,clk)
begin
if (rising_edge(clk)) then
if(sw(1)='1') then n1<=fout;
else n1<=n1;
end if;

if(sw(2)='1') then n2<=fout;
else n2<=n2;
end if;
end if;
end process;


--process(equals_debounced)
--begin
--    if equals_debounced = '1' then
--        show_result <= not show_result;
--    end if;
--end process;
show_result<=sw(3);
op<=sw(0);

Number1: entity WORK.numberReg port map(n1,rst,ld,sgn1,exp1,radix1);
Number2: entity WORK.numberReg port map(n2,rst,ld,sgn2,exp2,radix2);

Edge1: entity WORK.edge port map(exp1,subnormal1);
Edge2: entity WORK.edge port map(exp2,subnormal2);

Comparator_exponenti: entity WORK.comparator_min port map(exp1,exp2,min);

Concat_1: entity WORK.concat port map(radix1, subnormal1, radix_n1);
Concat_2: entity WORK.concat port map(radix2, subnormal2, radix_n2);

Exponent_maxim: entity WORK.mux_generic generic map(8) port map(exp1,exp2,min,exp_max);
Exponent_minim: entity WORK.mux_generic generic map(8) port map(exp2,exp1,min,exp_min);

Diferenta_exp: entity WORK.alu8 port map(exp_max, exp_min, dif);

Select_radix_min: entity WORK.mux_generic generic map(24) port map(radix_n2, radix_n1, min, radix_min);
Select_radix_max: entity WORK.mux_generic generic map(24) port map(radix_n1, radix_n2, min, radix_max);

dif_10bits <= "00"&dif;
shift_left_min_radix: entity WORK.shift_right_n generic map(24) port map(radix_min,dif_10bits,radix_shifted);

select_operands_order1: entity WORK.mux_generic generic map(24) port map(radix_max, radix_shifted, min, radix_entry_1);
select_operands_order2: entity WORK.mux_generic generic map(24) port map(radix_shifted, radix_max, min, radix_entry_2);

OANA1(0)<=sgn2;
OANA2(0)<=sgn1;


select_signs_order1: entity WORK.mux_generic generic map(1) port map(OANA1 ,  OANA2, min, sgn_entry_1);
select_signs_order2: entity WORK.mux_generic generic map(1) port map( OANA2,  OANA1, min, sgn_entry_2);

signs<=sgn1 & sgn2;

operation: entity WORK.alu port map(radix_entry_1,radix_entry_2,op,signs,zero,sign,result, overflow);

normalizare: entity WORK.normalizare port map(result, shift_exp,shifted_result);

shift_e: entity WORK.shift_exponent port map(exp_max, shift_exp,out_of_range,final_exp,overflow);

final_number<=x"00000000" when zero='1' else sign & final_exp & shifted_result(22 downto 0);


Data <=  final_number when show_result = '1' else fout;

displ7seg: entity WORK.displ7seg port map (
    Clk => Clk,
    Rst => Rst,
    Data => Data,
    An => An,
    Seg => Seg);

end Behavioral;