module processador(input [17:0] SW,
input[3:0]KEY, output logic [8:0]LEDG, output logic[17:0]LEDR,
output logic HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7,HEX8,
input CLOCK_50,
output logic R0,R1,R2,R3,R4,R5,R6,R7);

logic inte, RESET,M_CLOCK,SALVA,loadEn,MBSel,MDSel ;
logic [6:0] PC;
logic [1:0] modo,destinationSel,bSel,aSel;
logic [15:0] DOUT,dado,ConstantIn,Datain,DataIn,saidaULA,saidaShifter;
logic [15:0] BUSA,BUSB,BUSD;
logic [3:0] FsSel;
logic [15:0] display0,display1;
logic [15:0] ROM, REG, ramadd, ram_data;
logic [3:0] DA,AA,BA;
logic MD,RW,MW,PL,JB,BC,MB,MR,ramMW,ready;

always_comb
	inte <= SW[3];

clockAutomatico(CLOCK_50, KEY[1], LEDG[8]);

always_comb
	M_CLOCK <= LEDG[8];

rom(.address(PC),.clock(CLOCK_50),.q(ROM));
decodificador(ROM,DA,AA,BA,MB,MD,RW,MW,PL,FS0,BC,JB,MR);


datapath(RW,MB,FsSel[3]*FsSel[2],MD,M_CLOCK,RESET,DA,BA,AA,FsSel[1:0],ConstantIn,
		DataIn,FsSel,BUSD,saidaULA,saidaShifter,R0,R1,R2,R3,R4,R5,R6,R7,BUSA,
		BUSB,LEDG[7],LEDG[6],LEDG[5],LEDG[4]);

num2seg(display0, HEX3, HEX2, HEX1, HEX0);
num2seg(display1, HEX7, HEX6, HEX5, HEX4);

always_comb
	case(modo)
		0: begin
		  display0 <= BUSA;
		  display1 <= BUSB;
		end
		1: begin
			display0 <= saidaShifter;
			display1 <= saidaULA;
		end
		2: begin
			display0 <= 1'd0;
			display1 <= BUSD;
			end
		default: begin
				display0 <= PC;
				display1 <= ROM;
			end
	endcase



always_comb begin
	if ( BUSA[10] == 0 )
		DataIn <= Datain;
	else
		DataIn <= SW[2:0];
end

always_ff @(posedge M_CLOCK ) begin
	if ( (MW == 1) & (BUSA[10] == 1) )
	REG <= BUSB;
end

always_ff @(posedge M_CLOCK or posedge RESET) begin
	if (RESET)
	PC<=0;
	else begin
			if(~PL)
			   PC <= PC + 1;
			else if
			  ( JB == 1) PC <= DA;
	end
end

always_comb begin
	LEDG[3]<= REG[3];
	LEDG[2]<= REG[2];
	LEDG[1]<= REG[1];
	LEDG[0]<= REG[0];
	ConstantIn <= {13'b0000000000000,BA};
	FsSel[3] <= ROM[12];
	FsSel[2] <= ROM[11];
	FsSel[1] <= ROM[10];
	FsSel[0] <= FS0;
end

always_comb begin
	RESET <= ~KEY[0];
	SALVA <= KEY[2];
	modo <= SW[17:16];

	case (modo)
		0: LEDR[16:0] <= ConstantIn;
		1: LEDR[16:0] <= DataIn;
		2: LEDR[16:0] <= 0;
		default: begin
			LEDR[16:14] <= AA;
			LEDR[13:11] <= BA;
			LEDR[10] <= MB;
			LEDR[9:6]<= FsSel;
			LEDR[5] <= MD;
			LEDR[4] <= RW;
			LEDR[3] <= MW;
			LEDR[2] <= PL;
			LEDR[1] <= JB;
			LEDR[0] <= BC;
		end
	endcase
end


endmodule