Guest User

Untitled

a guest
Aug 18th, 2019
65
Never
Not a member of Pastebin yet? Sign Up, it unlocks many cool features!
  1. ----------------------------------------------------------------------------------
  2. -- Company: apertusĀ° Association
  3. -- Engineer: Apurva Nandan
  4. --
  5. -- Create Date: 00:22:57 08/05/2019
  6. -- Design Name:
  7. -- Module Name: ft601
  8. -- Project Name:
  9. -- Target Devices:
  10. -- Tool versions:
  11. -- Description: FT601 Controller in FT245 mode
  12. --
  13. -- Dependencies:
  14. --
  15. -- Revision:
  16. -- Revision 0.01 - File Created
  17. -- Additional Comments:
  18. --
  19. ----------------------------------------------------------------------------------
  20.  
  21. library ieee;
  22. use ieee.std_logic_1164.all;
  23. use ieee.std_logic_unsigned.all;
  24.  
  25. entity ft601 is
  26. port (
  27. clk : in std_logic;
  28. rst : in std_logic;
  29. led : out std_logic;
  30.  
  31. -- To FT601 chip
  32. ft601_data : inout std_logic_vector(31 downto 0);
  33. ft601_be : out std_logic_vector(3 downto 0);
  34. ft601_rxf_n : in std_logic;
  35. ft601_txe_n : in std_logic;
  36. ft601_wr_n : out std_logic;
  37. ft601_siwu_n : out std_logic;
  38. ft601_rd_n : out std_logic;
  39. ft601_oe_n : out std_logic;
  40.  
  41. -- From Internal FIFOs
  42. data_in : in std_logic_vector(31 downto 0);
  43. req_data : out std_logic;
  44. fifo_in_emp : in std_logic;
  45. data_wr_en : in std_logic
  46. );
  47.  
  48. end entity ft601;
  49.  
  50.  
  51. architecture rtl of ft601 is
  52. constant IDLE : std_logic_vector(2 downto 0) := "000";
  53. constant INTMDT1 : std_logic_vector(2 downto 0) := "001";
  54. constant INTMDT2 : std_logic_vector(2 downto 0) := "010";
  55. constant INTMDT3 : std_logic_vector(2 downto 0) := "011";
  56. constant ACTIVE_TX : std_logic_vector(2 downto 0) := "101";
  57.  
  58. --signal state : std_logic_vector(2 downto 0) := IDLE;
  59. signal ft601_txe : std_logic := '0';
  60. signal ft601_rxf : std_logic := '0';
  61. --signal rd_en : std_logic := '0';
  62. signal wr_en : std_logic := '0';
  63. --signal dat_rdy : std_logic := '0';
  64. signal dat_buf : std_logic_vector(31 downto 0);
  65. signal dat_o_buf : std_logic_vector(31 downto 0);
  66.  
  67. signal tx_state : std_logic_vector(2 downto 0) := IDLE;
  68. signal valid : std_logic_vector(2 downto 0) := "000";
  69. signal pre_valid : std_logic_vector(2 downto 0) := "000";
  70. signal data : std_logic_vector(95 downto 0);
  71. signal pre_data : std_logic_vector(95 downto 0);
  72.  
  73. begin
  74.  
  75. process(clk)
  76. begin
  77. if rising_edge(clk) then
  78. ft601_rxf <= not ft601_rxf_n;
  79. ft601_txe <= not ft601_txe_n;
  80. ft601_oe_n <= '1';
  81. ft601_rd_n <= '1';
  82.  
  83. end if;
  84. end process;
  85.  
  86. process(clk)
  87. begin
  88. if rising_edge(clk) then
  89. if rst = '1' then
  90. tx_state <= IDLE;
  91. wr_en <= '0';
  92. valid <= "000";
  93. pre_valid <= "000";
  94.  
  95. else
  96. if tx_state = IDLE then
  97. if ft601_txe = '1' and (pre_valid(0) = '1' or fifo_in_emp = '0') then
  98. tx_state <= ACTIVE_TX;
  99. dat_buf <= pre_data(31 downto 0);
  100. valid(2) <= pre_valid(0);
  101. wr_en <= pre_valid(0);
  102. pre_valid <= "0" & pre_valid(2 downto 1);
  103.  
  104. data(95 downto 64) <= pre_data(31 downto 0);
  105. pre_data(63 downto 0) <= pre_data(95 downto 32);
  106.  
  107. end if;
  108.  
  109. elsif tx_state = ACTIVE_TX then
  110. if ft601_txe = '0' or (pre_valid(1) = '0' and fifo_in_emp ='1') then
  111. tx_state <= INTMDT1;
  112.  
  113. end if;
  114.  
  115. if pre_valid(0) = '1' then
  116. data(95 downto 0) <= pre_data(31 downto 0) & data(95 downto 32);
  117. pre_data(63 downto 0) <= pre_data(95 downto 32);
  118. dat_buf <= pre_data(31 downto 0);
  119.  
  120. else
  121. data(95 downto 0) <= data_in & data(95 downto 32);
  122. pre_data(63 downto 0) <= pre_data(95 downto 32);
  123. dat_buf <= data_in;
  124.  
  125. end if;
  126. valid(2) <= pre_valid(0) or data_wr_en;
  127. valid(1) <= valid(2);
  128. valid(0) <= valid(1) and not ft601_txe;
  129.  
  130. wr_en <= pre_valid(0) or data_wr_en;
  131. pre_valid <= "0" & pre_valid(2 downto 1);
  132.  
  133. elsif tx_state = INTMDT1 then
  134. tx_state <= INTMDT2;
  135. wr_en <= '0';
  136. valid(1) <= valid(1) and not ft601_txe;
  137.  
  138. elsif tx_state = INTMDT2 then
  139. tx_state <= INTMDT3;
  140. valid(2) <= valid(2) and not ft601_txe;
  141.  
  142. elsif tx_state = INTMDT3 then
  143. valid <= valid(1 downto 0) & "0";
  144. data(95 downto 32) <= data( 63 downto 0);
  145.  
  146. if valid(1 downto 0) = "00" then
  147. tx_state <= IDLE;
  148.  
  149. end if;
  150.  
  151. if valid(2) = '1' then
  152. pre_valid <= pre_valid(1 downto 0) & valid(2);
  153. pre_data <= pre_data(63 downto 0) & data(95 downto 64);
  154.  
  155. end if;
  156. end if;
  157. end if;
  158. end if;
  159. end process;
  160.  
  161. ft601_data <= dat_buf(7 downto 0) & dat_buf(15 downto 8) & dat_buf(23 downto 16) & dat_buf(31 downto 24);
  162.  
  163. req_data <= (not fifo_in_emp) and ft601_txe and (not pre_valid(1)) when (tx_state = IDLE or tx_state = ACTIVE_TX) else '0';
  164. ft601_be <= "1111";
  165. ft601_siwu_n <= '1';
  166.  
  167. ft601_wr_n <= not wr_en;
  168.  
  169. led <= not rst when tx_state /= IDLE else '0';
  170.  
  171. end architecture rtl;
RAW Paste Data