Sreg_tb.sv

module sreg_tb;
logic tc;
logic td;
logic [7:0] tq;

Sreg N (
    .c(tc),
    .d(td),
    .q(tq)
);

initial begin
    tc = 0;
    #1
    tc = 1;
    td = 0;
    #1
    tc = 0;
    #1
    tc = 1;
    td = 1;
    #1
    tc = 0;
    #1
    tc = 1;
    td = 1;
    #1
    tc = 0;
    #1
    tc = 1;
    td = 0;
    #1
    tc = 0;
    #1
    tc = 1;
    td = 1;
    #1
    tc = 0;
    #1
    tc = 1;
    td = 0;
    #1
    tc = 0;
    #1
    tc = 1;
    td = 0;
    #1
    tc = 0;
    #1
    tc = 1;
    td = 0;
    #1
    tc = 0;
    $finish();
end

endmodule