from nmigen import *
from nmigen_boards import ecp5_5g_evn as FPGA

class Test(Elaboratable):
    def __init__(self, out=Signal()):
        self.out = out
        self.ports = [
            self.out,
        ]

    def elaborate(self, platform):
        m = Module()
        m.d.sync += self.out.eq(~self.out)
        return m

class MCVE(Elaboratable):
    def elaborate(self, platform):
        m = Module()

        s = Signal(4)
        for i in range(0, 4):
            m.submodules += Test(s[i])

        return m
FPGA.ECP55GEVNPlatform().build(MCVE(), do_program=True)