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0002-Add-ST7735R-MPU-LCD-support-for-iMX7D-board.patch

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  1. From c15b21915dde58240d32e8cf2f739cb115919f84 Mon Sep 17 00:00:00 2001
  2. From: b19715 <[email protected]>
  3. Date: Wed, 17 Oct 2018 14:24:10 -0400
  4. Subject: [PATCH 04/11] Add ST7735R MPU LCD support for iMX7D board
  5.  
  6. Updated for L4.9.11 release
  7. ---
  8. arch/arm/boot/dts/Makefile | 1 +
  9. arch/arm/boot/dts/imx7d-sdb-i80lcd.dts | 1059 +++++++++++++++++
  10. arch/arm/configs/imx_v7_defconfig | 1 +
  11. drivers/video/fbdev/mxc/Kconfig | 4 +
  12. drivers/video/fbdev/mxc/Makefile | 1 +
  13. .../video/fbdev/mxc/mxsfb_st7735r_square.c | 196 +++
  14. drivers/video/fbdev/mxsfb.c | 6 +
  15. drivers/video/fbdev/mxsfb.h | 7 +
  16. 8 files changed, 1275 insertions(+)
  17. create mode 100644 arch/arm/boot/dts/imx7d-sdb-i80lcd.dts
  18. create mode 100644 drivers/video/fbdev/mxc/mxsfb_st7735r_square.c
  19.  
  20. diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
  21. index 4969795383df..459f03a2fa00 100644
  22. --- a/arch/arm/boot/dts/Makefile
  23. +++ b/arch/arm/boot/dts/Makefile
  24. @@ -564,6 +564,7 @@ dtb-$(CONFIG_SOC_IMX7D) += \
  25. imx7d-12x12-lpddr3-arm2-pcie.dtb \
  26. imx7d-19x19-lpddr2-arm2.dtb \
  27. imx7d-sdb.dtb \
  28. + imx7d-sdb-i80lcd.dtb \
  29. imx7d-sdb-epdc.dtb \
  30. imx7d-sdb-gpmi-weim.dtb \
  31. imx7d-sdb-m4.dtb \
  32. diff --git a/arch/arm/boot/dts/imx7d-sdb-i80lcd.dts b/arch/arm/boot/dts/imx7d-sdb-i80lcd.dts
  33. new file mode 100644
  34. index 000000000000..4cb2b77eaf78
  35. --- /dev/null
  36. +++ b/arch/arm/boot/dts/imx7d-sdb-i80lcd.dts
  37. @@ -0,0 +1,1059 @@
  38. +/*
  39. + * Copyright (C) 2016 Freescale Semiconductor, Inc.
  40. + *
  41. + * This program is free software; you can redistribute it and/or modify
  42. + * it under the terms of the GNU General Public License version 2 as
  43. + * published by the Free Software Foundation.
  44. + */
  45. +
  46. +/dts-v1/;
  47. +
  48. +#include <dt-bindings/input/input.h>
  49. +#include "imx7d.dtsi"
  50. +
  51. +/ {
  52. + model = "Freescale i.MX7 SabreSD Board";
  53. + compatible = "fsl,imx7d-sdb", "fsl,imx7d";
  54. +
  55. + memory {
  56. + reg = <0x80000000 0x80000000>;
  57. + };
  58. +
  59. + backlight {
  60. + compatible = "pwm-backlight";
  61. + pwms = <&pwm1 0 5000000>;
  62. + brightness-levels = <0 4 8 16 32 64 128 255>;
  63. + default-brightness-level = <6>;
  64. + status = "okay";
  65. + };
  66. +
  67. + pxp_v4l2_out {
  68. + compatible = "fsl,imx7d-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2";
  69. + status = "okay";
  70. + };
  71. +
  72. + regulators {
  73. + compatible = "simple-bus";
  74. + #address-cells = <1>;
  75. + #size-cells = <0>;
  76. +
  77. + reg_usb_otg1_vbus: regulator@0 {
  78. + compatible = "regulator-fixed";
  79. + reg = <0>;
  80. + regulator-name = "usb_otg1_vbus";
  81. + regulator-min-microvolt = <5000000>;
  82. + regulator-max-microvolt = <5000000>;
  83. + gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
  84. + enable-active-high;
  85. + };
  86. +
  87. + reg_usb_otg2_vbus: regulator@1 {
  88. + compatible = "regulator-fixed";
  89. + reg = <1>;
  90. + regulator-name = "usb_otg2_vbus";
  91. + regulator-min-microvolt = <5000000>;
  92. + regulator-max-microvolt = <5000000>;
  93. + gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>;
  94. + enable-active-high;
  95. + };
  96. +
  97. + reg_can2_3v3: regulator@2 {
  98. + compatible = "regulator-fixed";
  99. + reg = <2>;
  100. + regulator-name = "can2-3v3";
  101. + regulator-min-microvolt = <3300000>;
  102. + regulator-max-microvolt = <3300000>;
  103. + gpio = <&gpio2 14 GPIO_ACTIVE_LOW>;
  104. + };
  105. +
  106. + reg_vref_1v8: regulator@3 {
  107. + compatible = "regulator-fixed";
  108. + regulator-name = "vref-1v8";
  109. + regulator-min-microvolt = <1800000>;
  110. + regulator-max-microvolt = <1800000>;
  111. + };
  112. +
  113. + reg_pcie: regulator@4 {
  114. + compatible = "regulator-fixed";
  115. + reg = <4>;
  116. + regulator-name = "MPCIE_3V3";
  117. + regulator-min-microvolt = <3300000>;
  118. + regulator-max-microvolt = <3300000>;
  119. + gpio = <&gpio_spi 6 GPIO_ACTIVE_HIGH>;
  120. + regulator-always-on;
  121. + enable-active-high;
  122. + };
  123. +
  124. + reg_sd1_vmmc: regulator@5 {
  125. + compatible = "regulator-fixed";
  126. + regulator-name = "VDD_SD1";
  127. + regulator-min-microvolt = <3300000>;
  128. + regulator-max-microvolt = <3300000>;
  129. + gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
  130. + startup-delay-us = <200000>;
  131. + enable-active-high;
  132. + };
  133. +
  134. + wlreg_on: fixedregulator@100 {
  135. + compatible = "regulator-fixed";
  136. + regulator-min-microvolt = <5000000>;
  137. + regulator-max-microvolt = <5000000>;
  138. + regulator-name = "wlreg_on";
  139. + gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
  140. + enable-active-high;
  141. + };
  142. + };
  143. +
  144. + bcmdhd_wlan_0: bcmdhd_wlan@0 {
  145. + compatible = "android,bcmdhd_wlan";
  146. + wlreg_on-supply = <&wlreg_on>;
  147. + };
  148. +
  149. + sound {
  150. + compatible = "fsl,imx7d-evk-wm8960",
  151. + "fsl,imx-audio-wm8960";
  152. + model = "wm8960-audio";
  153. + cpu-dai = <&sai1>;
  154. + audio-codec = <&codec>;
  155. + codec-master;
  156. + /* JD2: hp detect high for headphone*/
  157. + hp-det = <2 0>;
  158. + audio-routing =
  159. + "LINPUT1", "Main MIC",
  160. + "Main MIC", "MICB";
  161. + assigned-clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_SRC>,
  162. + <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
  163. + assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
  164. + assigned-clock-rates = <0>, <12288000>;
  165. +
  166. + };
  167. +
  168. + sound-hdmi {
  169. + compatible = "fsl,imx7d-sdb-sii902x",
  170. + "fsl,imx-audio-sii902x";
  171. + model = "sii902x-audio";
  172. + cpu-dai = <&sai1>;
  173. + hdmi-controler = <&sii902x>;
  174. + };
  175. +
  176. + spi4 {
  177. + compatible = "spi-gpio";
  178. + pinctrl-names = "default";
  179. + pinctrl-0 = <&pinctrl_spi1>;
  180. + status = "okay";
  181. + gpio-sck = <&gpio1 13 0>;
  182. + gpio-mosi = <&gpio1 9 0>;
  183. + cs-gpios = <&gpio1 12 0>;
  184. + num-chipselects = <1>;
  185. + #address-cells = <1>;
  186. + #size-cells = <0>;
  187. +
  188. + gpio_spi: gpio_spi@0 {
  189. + compatible = "fairchild,74hc595";
  190. + gpio-controller;
  191. + #gpio-cells = <2>;
  192. + reg = <0>;
  193. + registers-number = <1>;
  194. + registers-default = /bits/ 8 <0x54>; /* Enable PERI_3V3, SENSOR_RST_B and HDMI_RST*/
  195. + spi-max-frequency = <100000>;
  196. + };
  197. + };
  198. +};
  199. +
  200. +&adc1 {
  201. + vref-supply = <&reg_vref_1v8>;
  202. + status = "okay";
  203. +};
  204. +
  205. +&adc2 {
  206. + vref-supply = <&reg_vref_1v8>;
  207. + status = "okay";
  208. +};
  209. +
  210. +&clks {
  211. + assigned-clocks = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
  212. + assigned-clock-rates = <884736000>;
  213. +};
  214. +
  215. +&cpu0 {
  216. + arm-supply = <&sw1a_reg>;
  217. +};
  218. +
  219. +&csi1 {
  220. + csi-mux-mipi = <&gpr 0x14 4>;
  221. + status = "okay";
  222. +
  223. + port {
  224. + csi_ep: endpoint {
  225. + remote-endpoint = <&csi_mipi_ep>;
  226. + };
  227. + };
  228. +};
  229. +
  230. +&epdc {
  231. + pinctrl-names = "default";
  232. + pinctrl-0 = <&pinctrl_epdc0>;
  233. + V3P3-supply = <&V3P3_reg>;
  234. + VCOM-supply = <&VCOM_reg>;
  235. + DISPLAY-supply = <&DISPLAY_reg>;
  236. + en-gpios = <&gpio_spi 5 0>;
  237. + status = "disabled";
  238. +};
  239. +
  240. +&epxp {
  241. + status = "okay";
  242. +};
  243. +
  244. +&fec1 {
  245. + pinctrl-names = "default";
  246. + pinctrl-0 = <&pinctrl_enet1>;
  247. + pinctrl-assert-gpios = <&gpio_spi 5 GPIO_ACTIVE_HIGH>;
  248. + assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
  249. + <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
  250. + assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
  251. + assigned-clock-rates = <0>, <100000000>;
  252. + phy-mode = "rgmii";
  253. + phy-handle = <&ethphy0>;
  254. + fsl,magic-packet;
  255. + status = "okay";
  256. +
  257. + mdio {
  258. + #address-cells = <1>;
  259. + #size-cells = <0>;
  260. +
  261. + ethphy0: ethernet-phy@0 {
  262. + compatible = "ethernet-phy-ieee802.3-c22";
  263. + reg = <0>;
  264. + };
  265. +
  266. + ethphy1: ethernet-phy@1 {
  267. + compatible = "ethernet-phy-ieee802.3-c22";
  268. + reg = <1>;
  269. + };
  270. + };
  271. +};
  272. +
  273. +&fec2 {
  274. + pinctrl-names = "default";
  275. + pinctrl-0 = <&pinctrl_enet2>;
  276. + assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
  277. + <&clks IMX7D_ENET2_TIME_ROOT_CLK>;
  278. + assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
  279. + assigned-clock-rates = <0>, <100000000>;
  280. + phy-mode = "rgmii";
  281. + phy-handle = <&ethphy1>;
  282. + fsl,magic-packet;
  283. + status = "disabled";
  284. +};
  285. +
  286. +&flexcan2 {
  287. + pinctrl-names = "default";
  288. + pinctrl-0 = <&pinctrl_flexcan2>;
  289. + xceiver-supply = <&reg_can2_3v3>;
  290. + status = "okay";
  291. +};
  292. +
  293. +&gpmi {
  294. + pinctrl-names = "default";
  295. + pinctrl-0 = <&pinctrl_gpmi_nand_1>;
  296. + status = "disabled";
  297. + nand-on-flash-bbt;
  298. +};
  299. +
  300. +&mipi_csi {
  301. + clock-frequency = <240000000>;
  302. + status = "okay";
  303. + port {
  304. + mipi_sensor_ep: endpoint1 {
  305. + remote-endpoint = <&ov5647_mipi_ep>;
  306. + data-lanes = <2>;
  307. + csis-hs-settle = <13>;
  308. + csis-wclk;
  309. + };
  310. +
  311. + csi_mipi_ep: endpoint2 {
  312. + remote-endpoint = <&csi_ep>;
  313. + };
  314. + };
  315. +};
  316. +
  317. +&i2c1 {
  318. + clock-frequency = <100000>;
  319. + pinctrl-names = "default";
  320. + pinctrl-0 = <&pinctrl_i2c1>;
  321. + status = "okay";
  322. +
  323. + pmic: pfuze3000@08 {
  324. + compatible = "fsl,pfuze3000";
  325. + reg = <0x08>;
  326. +
  327. + regulators {
  328. + sw1a_reg: sw1a {
  329. + regulator-min-microvolt = <700000>;
  330. + regulator-max-microvolt = <3300000>;
  331. + regulator-boot-on;
  332. + regulator-always-on;
  333. + regulator-ramp-delay = <6250>;
  334. + };
  335. +
  336. + /* use sw1c_reg to align with pfuze100/pfuze200 */
  337. + sw1c_reg: sw1b {
  338. + regulator-min-microvolt = <700000>;
  339. + regulator-max-microvolt = <1475000>;
  340. + regulator-boot-on;
  341. + regulator-always-on;
  342. + regulator-ramp-delay = <6250>;
  343. + };
  344. +
  345. + sw2_reg: sw2 {
  346. + regulator-min-microvolt = <1500000>;
  347. + regulator-max-microvolt = <1850000>;
  348. + regulator-boot-on;
  349. + regulator-always-on;
  350. + };
  351. +
  352. + sw3a_reg: sw3 {
  353. + regulator-min-microvolt = <900000>;
  354. + regulator-max-microvolt = <1650000>;
  355. + regulator-boot-on;
  356. + regulator-always-on;
  357. + };
  358. +
  359. + swbst_reg: swbst {
  360. + regulator-min-microvolt = <5000000>;
  361. + regulator-max-microvolt = <5150000>;
  362. + };
  363. +
  364. + snvs_reg: vsnvs {
  365. + regulator-min-microvolt = <1000000>;
  366. + regulator-max-microvolt = <3000000>;
  367. + regulator-boot-on;
  368. + regulator-always-on;
  369. + };
  370. +
  371. + vref_reg: vrefddr {
  372. + regulator-boot-on;
  373. + regulator-always-on;
  374. + };
  375. +
  376. + vgen1_reg: vldo1 {
  377. + regulator-min-microvolt = <1800000>;
  378. + regulator-max-microvolt = <3300000>;
  379. + regulator-always-on;
  380. + };
  381. +
  382. + vgen2_reg: vldo2 {
  383. + regulator-min-microvolt = <800000>;
  384. + regulator-max-microvolt = <1550000>;
  385. + regulator-always-on;
  386. + };
  387. +
  388. + vgen3_reg: vccsd {
  389. + regulator-min-microvolt = <2850000>;
  390. + regulator-max-microvolt = <3300000>;
  391. + regulator-always-on;
  392. + };
  393. +
  394. + vgen4_reg: v33 {
  395. + regulator-min-microvolt = <2850000>;
  396. + regulator-max-microvolt = <3300000>;
  397. + regulator-always-on;
  398. + };
  399. +
  400. + vgen5_reg: vldo3 {
  401. + regulator-min-microvolt = <1800000>;
  402. + regulator-max-microvolt = <3300000>;
  403. + regulator-always-on;
  404. + };
  405. +
  406. + vgen6_reg: vldo4 {
  407. + regulator-min-microvolt = <1800000>;
  408. + regulator-max-microvolt = <3300000>;
  409. + regulator-always-on;
  410. + };
  411. + };
  412. + };
  413. +};
  414. +
  415. +&i2c2 {
  416. + clock-frequency = <100000>;
  417. + pinctrl-names = "default";
  418. + pinctrl-0 = <&pinctrl_i2c2>;
  419. + status = "okay";
  420. +
  421. + fxas2100x@20 {
  422. + compatible = "fsl,fxas2100x";
  423. + reg = <0x20>;
  424. + };
  425. +
  426. + fxos8700@1e {
  427. + compatible = "fsl,fxos8700";
  428. + reg = <0x1e>;
  429. + };
  430. +
  431. + mpl3115@60 {
  432. + compatible = "fsl,mpl3115";
  433. + reg = <0x60>;
  434. + };
  435. +};
  436. +
  437. +&i2c3 {
  438. + clock-frequency = <100000>;
  439. + pinctrl-names = "default";
  440. + pinctrl-0 = <&pinctrl_i2c3>;
  441. + status = "okay";
  442. +
  443. + max17135: max17135@48 {
  444. + pinctrl-names = "default";
  445. + pinctrl-0 = <&pinctrl_max17135>;
  446. + compatible = "maxim,max17135";
  447. + reg = <0x48>;
  448. + status = "disabled";
  449. +
  450. + vneg_pwrup = <1>;
  451. + gvee_pwrup = <2>;
  452. + vpos_pwrup = <10>;
  453. + gvdd_pwrup = <12>;
  454. + gvdd_pwrdn = <1>;
  455. + vpos_pwrdn = <2>;
  456. + gvee_pwrdn = <8>;
  457. + vneg_pwrdn = <10>;
  458. + gpio_pmic_pwrgood = <&gpio2 31 0>;
  459. + gpio_pmic_vcom_ctrl = <&gpio4 14 0>;
  460. + gpio_pmic_wakeup = <&gpio2 23 0>;
  461. + gpio_pmic_v3p3 = <&gpio2 30 0>;
  462. + gpio_pmic_intr = <&gpio2 22 0>;
  463. +
  464. + regulators {
  465. + DISPLAY_reg: DISPLAY {
  466. + regulator-name = "DISPLAY";
  467. + };
  468. +
  469. + GVDD_reg: GVDD {
  470. + /* 20v */
  471. + regulator-name = "GVDD";
  472. + };
  473. +
  474. + GVEE_reg: GVEE {
  475. + /* -22v */
  476. + regulator-name = "GVEE";
  477. + };
  478. +
  479. + HVINN_reg: HVINN {
  480. + /* -22v */
  481. + regulator-name = "HVINN";
  482. + };
  483. +
  484. + HVINP_reg: HVINP {
  485. + /* 20v */
  486. + regulator-name = "HVINP";
  487. + };
  488. +
  489. + VCOM_reg: VCOM {
  490. + regulator-name = "VCOM";
  491. + /* 2's-compliment, -4325000 */
  492. + regulator-min-microvolt = <0xffbe0178>;
  493. + /* 2's-compliment, -500000 */
  494. + regulator-max-microvolt = <0xfff85ee0>;
  495. + };
  496. +
  497. + VNEG_reg: VNEG {
  498. + /* -15v */
  499. + regulator-name = "VNEG";
  500. + };
  501. +
  502. + VPOS_reg: VPOS {
  503. + /* 15v */
  504. + regulator-name = "VPOS";
  505. + };
  506. +
  507. + V3P3_reg: V3P3 {
  508. + regulator-name = "V3P3";
  509. + };
  510. + };
  511. + };
  512. +
  513. + sii902x: sii902x@39 {
  514. + compatible = "SiI,sii902x";
  515. + pinctrl-names = "default";
  516. + pinctrl-0 = <&pinctrl_sii902x>;
  517. + interrupt-parent = <&gpio2>;
  518. + interrupts = <13 IRQ_TYPE_EDGE_FALLING>;
  519. + mode_str ="1280x720M@60";
  520. + bits-per-pixel = <16>;
  521. + reg = <0x39>;
  522. + status = "okay";
  523. + };
  524. +};
  525. +
  526. +&i2c4 {
  527. + clock-frequency = <100000>;
  528. + pinctrl-names = "default";
  529. + pinctrl-0 = <&pinctrl_i2c4>;
  530. + status = "okay";
  531. +
  532. + codec: wm8960@1a {
  533. + compatible = "wlf,wm8960";
  534. + reg = <0x1a>;
  535. + clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
  536. + clock-names = "mclk";
  537. + wlf,shared-lrclk;
  538. + };
  539. +
  540. + ov5647_mipi: ov5647_mipi@36 {
  541. + compatible = "ovti,ov5647_mipi";
  542. + reg = <0x36>;
  543. + clocks = <&clks IMX7D_CLK_DUMMY>;
  544. + clock-names = "csi_mclk";
  545. + csi_id = <0>;
  546. + pwn-gpios = <&gpio_spi 7 GPIO_ACTIVE_HIGH>;
  547. + mclk = <24000000>;
  548. + mclk_source = <0>;
  549. + port {
  550. + ov5647_mipi_ep: endpoint {
  551. + remote-endpoint = <&mipi_sensor_ep>;
  552. + };
  553. + };
  554. + };
  555. +};
  556. +
  557. +&iomuxc {
  558. + pinctrl-names = "default";
  559. + pinctrl-0 = <&pinctrl_hog_1>;
  560. +
  561. + imx7d-sdb {
  562. + pinctrl_hog_1: hoggrp-1 {
  563. + fsl,pins = <
  564. + MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14
  565. + MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x80000000 /* bt reg on */
  566. + MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x59 /* VSELECT */
  567. + MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */
  568. + MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */
  569. + MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 /* vmmc */
  570. + >;
  571. + };
  572. +
  573. + pinctrl_epdc0: epdcgrp0 {
  574. + fsl,pins = <
  575. + MX7D_PAD_EPDC_DATA00__EPDC_DATA0 0x2
  576. + MX7D_PAD_EPDC_DATA01__EPDC_DATA1 0x2
  577. + MX7D_PAD_EPDC_DATA02__EPDC_DATA2 0x2
  578. + MX7D_PAD_EPDC_DATA03__EPDC_DATA3 0x2
  579. + MX7D_PAD_EPDC_DATA04__EPDC_DATA4 0x2
  580. + MX7D_PAD_EPDC_DATA05__EPDC_DATA5 0x2
  581. + MX7D_PAD_EPDC_DATA06__EPDC_DATA6 0x2
  582. + MX7D_PAD_EPDC_DATA07__EPDC_DATA7 0x2
  583. + MX7D_PAD_EPDC_DATA08__EPDC_DATA8 0x2
  584. + MX7D_PAD_EPDC_DATA09__EPDC_DATA9 0x2
  585. + MX7D_PAD_EPDC_DATA10__EPDC_DATA10 0x2
  586. + MX7D_PAD_EPDC_DATA11__EPDC_DATA11 0x2
  587. + MX7D_PAD_EPDC_DATA12__EPDC_DATA12 0x2
  588. + MX7D_PAD_EPDC_DATA13__EPDC_DATA13 0x2
  589. + MX7D_PAD_EPDC_DATA14__EPDC_DATA14 0x2
  590. + MX7D_PAD_EPDC_DATA15__EPDC_DATA15 0x2
  591. + MX7D_PAD_EPDC_SDCLK__EPDC_SDCLK 0x2
  592. + MX7D_PAD_EPDC_SDLE__EPDC_SDLE 0x2
  593. + MX7D_PAD_EPDC_SDOE__EPDC_SDOE 0x2
  594. + MX7D_PAD_EPDC_SDSHR__EPDC_SDSHR 0x2
  595. + MX7D_PAD_EPDC_SDCE0__EPDC_SDCE0 0x2
  596. + MX7D_PAD_EPDC_SDCE1__EPDC_SDCE1 0x2
  597. + MX7D_PAD_EPDC_GDCLK__EPDC_GDCLK 0x2
  598. + MX7D_PAD_EPDC_GDOE__EPDC_GDOE 0x2
  599. + MX7D_PAD_EPDC_GDRL__EPDC_GDRL 0x2
  600. + MX7D_PAD_EPDC_GDSP__EPDC_GDSP 0x2
  601. + MX7D_PAD_EPDC_BDR0__EPDC_BDR0 0x2
  602. + MX7D_PAD_EPDC_BDR1__EPDC_BDR1 0x2
  603. + >;
  604. + };
  605. +
  606. + pinctrl_enet1: enet1grp {
  607. + fsl,pins = <
  608. + MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x3
  609. + MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x3
  610. + MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1
  611. + MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1
  612. + MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1
  613. + MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1
  614. + MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1
  615. + MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1
  616. + MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1
  617. + MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1
  618. + MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1
  619. + MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1
  620. + MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1
  621. + MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1
  622. + >;
  623. + };
  624. +
  625. + pinctrl_enet2: enet2grp {
  626. + fsl,pins = <
  627. + MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x1
  628. + MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x1
  629. + MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x1
  630. + MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x1
  631. + MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x1
  632. + MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x1
  633. + MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x1
  634. + MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x1
  635. + MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x1
  636. + MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x1
  637. + MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x1
  638. + MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x1
  639. + >;
  640. + };
  641. +
  642. + pinctrl_ecspi3_cs: ecspi3_cs_grp {
  643. + fsl,pins = <
  644. + MX7D_PAD_SD2_CD_B__GPIO5_IO9 0x80000000
  645. + >;
  646. + };
  647. +
  648. + pinctrl_ecspi3: ecspi3grp {
  649. + fsl,pins = <
  650. + MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO 0x2
  651. + MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI 0x2
  652. + MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK 0x2
  653. + >;
  654. + };
  655. +
  656. + pinctrl_tsc2046_pendown: tsc2046_pendown {
  657. + fsl,pins = <
  658. + MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x59
  659. + >;
  660. + };
  661. +
  662. + pinctrl_flexcan2: flexcan2grp {
  663. + fsl,pins = <
  664. + MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x59
  665. + MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x59
  666. + >;
  667. + };
  668. +
  669. + pinctrl_gpmi_nand_1: gpmi-nand-1 {
  670. + fsl,pins = <
  671. + MX7D_PAD_SD3_CLK__NAND_CLE 0x71
  672. + MX7D_PAD_SD3_CMD__NAND_ALE 0x71
  673. + MX7D_PAD_SAI1_MCLK__NAND_WP_B 0x71
  674. + MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B 0x71
  675. + MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B 0x71
  676. + MX7D_PAD_SAI1_TX_DATA__NAND_READY_B 0x74
  677. + MX7D_PAD_SD3_STROBE__NAND_RE_B 0x71
  678. + MX7D_PAD_SD3_RESET_B__NAND_WE_B 0x71
  679. + MX7D_PAD_SD3_DATA0__NAND_DATA00 0x71
  680. + MX7D_PAD_SD3_DATA1__NAND_DATA01 0x71
  681. + MX7D_PAD_SD3_DATA2__NAND_DATA02 0x71
  682. + MX7D_PAD_SD3_DATA3__NAND_DATA03 0x71
  683. + MX7D_PAD_SD3_DATA4__NAND_DATA04 0x71
  684. + MX7D_PAD_SD3_DATA5__NAND_DATA05 0x71
  685. + MX7D_PAD_SD3_DATA6__NAND_DATA06 0x71
  686. + MX7D_PAD_SD3_DATA7__NAND_DATA07 0x71
  687. +
  688. + >;
  689. + };
  690. +
  691. + pinctrl_i2c1: i2c1grp {
  692. + fsl,pins = <
  693. + MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f
  694. + MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f
  695. + >;
  696. + };
  697. +
  698. + pinctrl_i2c2: i2c2grp {
  699. + fsl,pins = <
  700. + MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f
  701. + MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f
  702. + >;
  703. + };
  704. +
  705. + pinctrl_i2c3: i2c3grp {
  706. + fsl,pins = <
  707. + MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f
  708. + MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f
  709. + >;
  710. + };
  711. +
  712. + pinctrl_i2c4: i2c4grp {
  713. + fsl,pins = <
  714. + MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA 0x4000007f
  715. + MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL 0x4000007f
  716. + >;
  717. + };
  718. +
  719. + pinctrl_lcdif_dat: lcdifdatgrp {
  720. + fsl,pins = <
  721. + MX7D_PAD_EPDC_DATA00__LCD_DATA0 0x79
  722. + MX7D_PAD_EPDC_DATA01__LCD_DATA1 0x79
  723. + MX7D_PAD_EPDC_DATA02__LCD_DATA2 0x79
  724. + MX7D_PAD_EPDC_DATA03__LCD_DATA3 0x79
  725. + MX7D_PAD_EPDC_DATA04__LCD_DATA4 0x79
  726. + MX7D_PAD_EPDC_DATA05__LCD_DATA5 0x79
  727. + MX7D_PAD_EPDC_DATA06__LCD_DATA6 0x79
  728. + MX7D_PAD_EPDC_DATA07__LCD_DATA7 0x79
  729. + >;
  730. + };
  731. +
  732. + pinctrl_lcdif_ctrl: lcdifctrlgrp {
  733. + fsl,pins = <
  734. + MX7D_PAD_EPDC_GDRL__LCD_RD_E 0x79
  735. + MX7D_PAD_EPDC_GDOE__LCD_WR_RWN 0x79
  736. + MX7D_PAD_EPDC_BDR0__LCD_CS 0x79
  737. + MX7D_PAD_LCD_RESET__LCD_RESET 0x79
  738. + MX7D_PAD_EPDC_DATA08__GPIO2_IO8 0x79
  739. + >;
  740. + };
  741. +
  742. + pinctrl_max17135: max17135grp-1 {
  743. + fsl,pins = <
  744. + MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 0x80000000 /* pwrgood */
  745. + MX7D_PAD_I2C4_SCL__GPIO4_IO14 0x80000000 /* vcom_ctrl */
  746. + MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 0x80000000 /* wakeup */
  747. + MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x80000000 /* v3p3 */
  748. + MX7D_PAD_EPDC_SDCE2__GPIO2_IO22 0x80000000 /* pwr int */
  749. + >;
  750. + };
  751. +
  752. + pinctrl_sii902x: hdmigrp-1 {
  753. + fsl,pins = <
  754. + MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x59
  755. + >;
  756. + };
  757. +
  758. + pinctrl_sim1_1: sim1grp-1 {
  759. + fsl,pins = <
  760. + MX7D_PAD_EPDC_DATA10__SIM1_PORT1_RST_B 0x77
  761. + MX7D_PAD_EPDC_DATA12__SIM1_PORT1_PD 0x77
  762. + MX7D_PAD_EPDC_DATA11__SIM1_PORT1_SVEN 0x77
  763. + MX7D_PAD_EPDC_DATA09__SIM1_PORT1_CLK 0x73
  764. + MX7D_PAD_EPDC_DATA08__SIM1_PORT1_TRXD 0x73
  765. + >;
  766. + };
  767. +
  768. + pinctrl_uart1: uart1grp {
  769. + fsl,pins = <
  770. + MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79
  771. + MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79
  772. + >;
  773. + };
  774. +
  775. + pinctrl_uart5: uart5grp {
  776. + fsl,pins = <
  777. + MX7D_PAD_SAI1_TX_BCLK__UART5_DCE_TX 0x79
  778. + MX7D_PAD_SAI1_RX_DATA__UART5_DCE_RX 0x79
  779. + MX7D_PAD_SAI1_TX_SYNC__UART5_DCE_CTS 0x79
  780. + MX7D_PAD_SAI1_TX_DATA__UART5_DCE_RTS 0x79
  781. + >;
  782. + };
  783. +
  784. + pinctrl_uart5dte: uart5dtegrp {
  785. + fsl,pins = <
  786. + MX7D_PAD_SAI1_TX_BCLK__UART5_DTE_RX 0x79
  787. + MX7D_PAD_SAI1_RX_DATA__UART5_DTE_TX 0x79
  788. + MX7D_PAD_SAI1_TX_SYNC__UART5_DTE_RTS 0x79
  789. + MX7D_PAD_SAI1_TX_DATA__UART5_DTE_CTS 0x79
  790. + >;
  791. + };
  792. +
  793. + pinctrl_uart6: uart6grp {
  794. + fsl,pins = <
  795. + MX7D_PAD_ECSPI1_MOSI__UART6_DCE_TX 0x79
  796. + MX7D_PAD_ECSPI1_SCLK__UART6_DCE_RX 0x79
  797. + MX7D_PAD_ECSPI1_SS0__UART6_DCE_CTS 0x79
  798. + MX7D_PAD_ECSPI1_MISO__UART6_DCE_RTS 0x79
  799. + >;
  800. + };
  801. +
  802. + pinctrl_usdhc1: usdhc1grp {
  803. + fsl,pins = <
  804. + MX7D_PAD_SD1_CMD__SD1_CMD 0x59
  805. + MX7D_PAD_SD1_CLK__SD1_CLK 0x19
  806. + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59
  807. + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
  808. + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
  809. + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
  810. + >;
  811. + };
  812. +
  813. + pinctrl_usdhc1_100mhz: usdhc1grp_100mhz {
  814. + fsl,pins = <
  815. + MX7D_PAD_SD1_CMD__SD1_CMD 0x5a
  816. + MX7D_PAD_SD1_CLK__SD1_CLK 0x1a
  817. + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a
  818. + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a
  819. + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a
  820. + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a
  821. + >;
  822. + };
  823. +
  824. + pinctrl_usdhc1_200mhz: usdhc1grp_200mhz {
  825. + fsl,pins = <
  826. + MX7D_PAD_SD1_CMD__SD1_CMD 0x5b
  827. + MX7D_PAD_SD1_CLK__SD1_CLK 0x1b
  828. + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b
  829. + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b
  830. + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b
  831. + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b
  832. + >;
  833. + };
  834. +
  835. + pinctrl_usdhc2: usdhc2grp {
  836. + fsl,pins = <
  837. + MX7D_PAD_SD2_CMD__SD2_CMD 0x59
  838. + MX7D_PAD_SD2_CLK__SD2_CLK 0x19
  839. + MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59
  840. + MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59
  841. + MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59
  842. + MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59
  843. + MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x59 /* WL_REG_ON */
  844. + >;
  845. + };
  846. +
  847. + pinctrl_usdhc2_100mhz: usdhc2grp_100mhz {
  848. + fsl,pins = <
  849. + MX7D_PAD_SD2_CMD__SD2_CMD 0x5a
  850. + MX7D_PAD_SD2_CLK__SD2_CLK 0x1a
  851. + MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5a
  852. + MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5a
  853. + MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5a
  854. + MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5a
  855. + >;
  856. + };
  857. +
  858. + pinctrl_usdhc2_200mhz: usdhc2grp_200mhz {
  859. + fsl,pins = <
  860. + MX7D_PAD_SD2_CMD__SD2_CMD 0x5b
  861. + MX7D_PAD_SD2_CLK__SD2_CLK 0x1b
  862. + MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5b
  863. + MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5b
  864. + MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5b
  865. + MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5b
  866. + >;
  867. + };
  868. +
  869. + pinctrl_usdhc3: usdhc3grp {
  870. + fsl,pins = <
  871. + MX7D_PAD_SD3_CMD__SD3_CMD 0x59
  872. + MX7D_PAD_SD3_CLK__SD3_CLK 0x19
  873. + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59
  874. + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59
  875. + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
  876. + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59
  877. + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59
  878. + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59
  879. + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59
  880. + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59
  881. + MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19
  882. + >;
  883. + };
  884. +
  885. + pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
  886. + fsl,pins = <
  887. + MX7D_PAD_SD3_CMD__SD3_CMD 0x5a
  888. + MX7D_PAD_SD3_CLK__SD3_CLK 0x1a
  889. + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a
  890. + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a
  891. + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a
  892. + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a
  893. + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a
  894. + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a
  895. + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a
  896. + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a
  897. + MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a
  898. + >;
  899. + };
  900. +
  901. + pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
  902. + fsl,pins = <
  903. + MX7D_PAD_SD3_CMD__SD3_CMD 0x5b
  904. + MX7D_PAD_SD3_CLK__SD3_CLK 0x1b
  905. + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b
  906. + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b
  907. + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b
  908. + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b
  909. + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b
  910. + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b
  911. + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b
  912. + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b
  913. + MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b
  914. + >;
  915. + };
  916. +
  917. + pinctrl_sai1: sai1grp {
  918. + fsl,pins = <
  919. + MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x1f
  920. + MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK 0x1f
  921. + MX7D_PAD_ENET1_CRS__SAI1_TX_SYNC 0x1f
  922. + MX7D_PAD_ENET1_COL__SAI1_TX_DATA0 0x30
  923. + MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0 0x1f
  924. + >;
  925. + };
  926. +
  927. + pinctrl_sai2: sai2grp {
  928. + fsl,pins = <
  929. + MX7D_PAD_SAI2_TX_BCLK__SAI2_TX_BCLK 0x1f
  930. + MX7D_PAD_SAI2_TX_SYNC__SAI2_TX_SYNC 0x1f
  931. + MX7D_PAD_SAI2_TX_DATA__SAI2_TX_DATA0 0x30
  932. + MX7D_PAD_SAI2_RX_DATA__SAI2_RX_DATA0 0x1f
  933. + >;
  934. + };
  935. +
  936. + pinctrl_spi1: spi1grp {
  937. + fsl,pins = <
  938. + MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x59
  939. + MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x59
  940. + MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x59
  941. + >;
  942. + };
  943. + };
  944. +};
  945. +
  946. +&iomuxc_lpsr {
  947. + pinctrl-names = "default";
  948. + pinctrl-0 = <&pinctrl_hog_2>;
  949. +
  950. + imx7d-sdb {
  951. + pinctrl_hog_2: hoggrp-2 {
  952. + fsl,pins = <
  953. + MX7D_PAD_GPIO1_IO05__GPIO1_IO5 0x14
  954. + MX7D_PAD_EPDC_DATA14__GPIO2_IO14 0x59 /* CAN_STBY */
  955. + MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_B 0x74
  956. + >;
  957. + };
  958. +
  959. + pinctrl_pwm1: pwm1grp {
  960. + fsl,pins = <
  961. + MX7D_PAD_GPIO1_IO01__PWM1_OUT 0x110b0
  962. + >;
  963. + };
  964. + };
  965. +};
  966. +
  967. +&lcdif {
  968. + pinctrl-names = "default";
  969. + pinctrl-0 = <&pinctrl_lcdif_dat
  970. + &pinctrl_lcdif_ctrl>;
  971. + display = <&display0>;
  972. + status = "okay";
  973. +
  974. + display0: display {
  975. + mpu-mode;
  976. + lcd_rs_gpio = <&gpio2 8 0>;
  977. + lcd_panel = "ST7735R-SQUARE";
  978. + };
  979. +};
  980. +
  981. +&pcie {
  982. + pinctrl-names = "default";
  983. + reset-gpio = <&gpio_spi 1 GPIO_ACTIVE_LOW>;
  984. + disable-gpio = <&gpio_spi 0 GPIO_ACTIVE_LOW>;
  985. + status = "okay";
  986. +};
  987. +
  988. +&pwm1 {
  989. + pinctrl-names = "default";
  990. + pinctrl-0 = <&pinctrl_pwm1>;
  991. + status = "okay";
  992. +};
  993. +
  994. +&sai1 {
  995. + pinctrl-names = "default";
  996. + pinctrl-0 = <&pinctrl_sai1>;
  997. + assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
  998. + <&clks IMX7D_SAI1_ROOT_CLK>;
  999. + assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
  1000. + assigned-clock-rates = <0>, <36864000>;
  1001. + status = "okay";
  1002. +};
  1003. +
  1004. +&sdma {
  1005. + status = "okay";
  1006. +};
  1007. +
  1008. +&sim1 {
  1009. + pinctrl-names = "default";
  1010. + pinctrl-0 = <&pinctrl_sim1_1>;
  1011. + port = <0>;
  1012. + sven_low_active;
  1013. + status = "disabled";
  1014. +};
  1015. +
  1016. +&uart1 {
  1017. + pinctrl-names = "default";
  1018. + pinctrl-0 = <&pinctrl_uart1>;
  1019. + assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
  1020. + assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
  1021. + status = "okay";
  1022. +};
  1023. +
  1024. +&uart5 {
  1025. + pinctrl-names = "default";
  1026. + pinctrl-0 = <&pinctrl_uart5>;
  1027. + assigned-clocks = <&clks IMX7D_UART5_ROOT_SRC>;
  1028. + assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
  1029. + fsl,uart-has-rtscts;
  1030. + /* for DTE mode, add below change */
  1031. + /* fsl,dte-mode; */
  1032. + /* pinctrl-0 = <&pinctrl_uart5dte>; */
  1033. + status = "okay";
  1034. +};
  1035. +
  1036. +&uart6 {
  1037. + pinctrl-names = "default";
  1038. + pinctrl-0 = <&pinctrl_uart6>;
  1039. + assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
  1040. + assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
  1041. + fsl,uart-has-rtscts;
  1042. + status = "okay";
  1043. +};
  1044. +
  1045. +&usbotg1 {
  1046. + vbus-supply = <&reg_usb_otg1_vbus>;
  1047. + srp-disable;
  1048. + hnp-disable;
  1049. + adp-disable;
  1050. + status = "okay";
  1051. +};
  1052. +
  1053. +&usbotg2 {
  1054. + vbus-supply = <&reg_usb_otg2_vbus>;
  1055. + dr_mode = "host";
  1056. + status = "okay";
  1057. +};
  1058. +
  1059. +&usdhc1 {
  1060. + pinctrl-names = "default", "state_100mhz", "state_200mhz";
  1061. + pinctrl-0 = <&pinctrl_usdhc1>;
  1062. + pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
  1063. + pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
  1064. + cd-gpios = <&gpio5 0 0>;
  1065. + wp-gpios = <&gpio5 1 0>;
  1066. + tuning-step = <2>;
  1067. + vmmc-supply = <&reg_sd1_vmmc>;
  1068. + enable-sdio-wakeup;
  1069. + keep-power-in-suspend;
  1070. + status = "okay";
  1071. +};
  1072. +
  1073. +&usdhc2 {
  1074. + pinctrl-names = "default", "state_100mhz", "state_200mhz";
  1075. + pinctrl-0 = <&pinctrl_usdhc2>;
  1076. + pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
  1077. + pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
  1078. + enable-sdio-wakeup;
  1079. + keep-power-in-suspend;
  1080. + tuning-step = <2>;
  1081. + wifi-host;
  1082. + status = "okay";
  1083. +};
  1084. +
  1085. +&usdhc3 {
  1086. + pinctrl-names = "default", "state_100mhz", "state_200mhz";
  1087. + pinctrl-0 = <&pinctrl_usdhc3>;
  1088. + pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
  1089. + pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
  1090. + assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
  1091. + assigned-clock-rates = <400000000>;
  1092. + bus-width = <8>;
  1093. + tuning-step = <2>;
  1094. + non-removable;
  1095. + status = "okay";
  1096. +};
  1097. diff --git a/arch/arm/configs/imx_v7_defconfig b/arch/arm/configs/imx_v7_defconfig
  1098. index 98b3ba8db058..cfbbc939bbee 100644
  1099. --- a/arch/arm/configs/imx_v7_defconfig
  1100. +++ b/arch/arm/configs/imx_v7_defconfig
  1101. @@ -247,6 +247,7 @@ CONFIG_FB_MXC_LDB=y
  1102. CONFIG_FB_MXC_HDMI=y
  1103. CONFIG_FB_MXS_SII902X=y
  1104. CONFIG_FB_MXS_ST7789S_QVGA=y
  1105. +CONFIG_FB_MXS_ST7735R_SQUARE=y
  1106. CONFIG_FB_MXC_DCIC=m
  1107. CONFIG_FB_MXC_ADV7535=y
  1108. CONFIG_HANNSTAR_CABC=y
  1109. diff --git a/drivers/video/fbdev/mxc/Kconfig b/drivers/video/fbdev/mxc/Kconfig
  1110. index a34c52393069..9762404c010c 100644
  1111. --- a/drivers/video/fbdev/mxc/Kconfig
  1112. +++ b/drivers/video/fbdev/mxc/Kconfig
  1113. @@ -83,6 +83,10 @@ config FB_MXS_ST7789S_QVGA
  1114. tristate "ST7789S QVGA MPU Display"
  1115. depends on FB_MXS
  1116.  
  1117. +config FB_MXS_ST7735R_SQUARE
  1118. + tristate "ST7735R SQUARE MPU Display"
  1119. + depends on FB_MXS
  1120. +
  1121. config FB_MXC_DCIC
  1122. tristate "MXC DCIC"
  1123. depends on FB_MXC_SYNC_PANEL
  1124. diff --git a/drivers/video/fbdev/mxc/Makefile b/drivers/video/fbdev/mxc/Makefile
  1125. index 81650ec53fcf..34c6e6249a1a 100644
  1126. --- a/drivers/video/fbdev/mxc/Makefile
  1127. +++ b/drivers/video/fbdev/mxc/Makefile
  1128. @@ -13,5 +13,6 @@ obj-$(CONFIG_FB_MXC_EINK_PANEL) += mxc_epdc_fb.o
  1129. obj-$(CONFIG_FB_MXC_EINK_V2_PANEL) += mxc_epdc_v2_fb.o
  1130. obj-$(CONFIG_FB_MXS_SII902X) += mxsfb_sii902x.o
  1131. obj-$(CONFIG_FB_MXS_ST7789S_QVGA) += mxsfb_st7789s_qvga.o
  1132. +obj-$(CONFIG_FB_MXS_ST7735R_SQUARE) += mxsfb_st7735r_square.o
  1133. obj-$(CONFIG_FB_MXC_DCIC) += mxc_dcic.o
  1134. obj-$(CONFIG_HANNSTAR_CABC) += hannstar_cabc.o
  1135. diff --git a/drivers/video/fbdev/mxc/mxsfb_st7735r_square.c b/drivers/video/fbdev/mxc/mxsfb_st7735r_square.c
  1136. new file mode 100644
  1137. index 000000000000..f45712bbce52
  1138. --- /dev/null
  1139. +++ b/drivers/video/fbdev/mxc/mxsfb_st7735r_square.c
  1140. @@ -0,0 +1,196 @@
  1141. +/*
  1142. + * Copyright (C) 2016 Freescale Semiconductor, Inc. All Rights Reserved.
  1143. + *
  1144. + * This program is free software; you can redistribute it and/or modify
  1145. + * it under the terms of the GNU General Public License as published by
  1146. + * the Free Software Foundation; either version 2 of the License, or
  1147. + * (at your option) any later version.
  1148. +
  1149. + * This program is distributed in the hope that it will be useful,
  1150. + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  1151. + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  1152. + * GNU General Public License for more details.
  1153. +
  1154. + * You should have received a copy of the GNU General Public License along
  1155. + * with this program; if not, write to the Free Software Foundation, Inc.,
  1156. + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  1157. + */
  1158. +
  1159. +#include <linux/types.h>
  1160. +#include <linux/init.h>
  1161. +#include <linux/delay.h>
  1162. +#include <linux/err.h>
  1163. +#include <linux/io.h>
  1164. +
  1165. +#include "../mxsfb.h"
  1166. +
  1167. +static struct fb_videomode st7735r_lcd_modedb[] = {
  1168. + {
  1169. + "ST7735R-SQUARE", 60, 128, 128, 200000,
  1170. + 0, 0,
  1171. + 0, 0,
  1172. + 0, 0,
  1173. + 0,
  1174. + FB_VMODE_NONINTERLACED,
  1175. + 0,
  1176. + },
  1177. +};
  1178. +
  1179. +static struct mpu_lcd_config lcd_config = {
  1180. + .bus_mode = MPU_BUS_8080,
  1181. + .interface_width = 8,
  1182. + .panel_bpp = 16,
  1183. +};
  1184. +void mpu_st7735r_get_lcd_videomode(struct fb_videomode **mode, int *size,
  1185. + struct mpu_lcd_config **data)
  1186. +{
  1187. + *mode = &st7735r_lcd_modedb[0];
  1188. + *size = ARRAY_SIZE(st7735r_lcd_modedb);
  1189. + *data = &lcd_config;
  1190. +}
  1191. +
  1192. +int mpu_st7735r_lcd_setup(struct mxsfb_info * mxsfb)
  1193. +{
  1194. + unsigned int val;
  1195. +
  1196. + if (mxsfb == NULL)
  1197. + return -1;
  1198. +
  1199. + /* Software reset */
  1200. + mxsfb_mpu_access(mxsfb, MPU_CMD, MPU_WRITE, 0x01);
  1201. + msleep(120);
  1202. +
  1203. + /* Read display ID */
  1204. + mxsfb_mpu_access(mxsfb, MPU_CMD, MPU_WRITE, 0x04);
  1205. + val = mxsfb_mpu_access(mxsfb, MPU_DATA, MPU_READ, 0x00);
  1206. + val = mxsfb_mpu_access(mxsfb, MPU_DATA, MPU_READ, 0x00);
  1207. + printk(KERN_INFO "Manufacturer ID = 0x%02x.\n", val);
  1208. + val = mxsfb_mpu_access(mxsfb, MPU_DATA, MPU_READ, 0x00);
  1209. + printk(KERN_INFO "Driver version ID = 0x%02x.\n", val);
  1210. + val = mxsfb_mpu_access(mxsfb, MPU_DATA, MPU_READ, 0x00);
  1211. + printk(KERN_INFO "Driver ID = 0x%02x.\n", val);
  1212. +
  1213. + /* Sleep out */
  1214. + mxsfb_mpu_access(mxsfb, MPU_CMD, MPU_WRITE, 0x11);
  1215. + msleep(120);
  1216. +
  1217. + /* Set frame rate */
  1218. + mxsfb_mpu_access(mxsfb, MPU_CMD, MPU_WRITE, 0xB1);
  1219. + mxsfb_mpu_access(mxsfb, MPU_DATA, MPU_WRITE, 0x00);
  1220. + mxsfb_mpu_access(mxsfb, MPU_DATA, MPU_WRITE, 0x08);
  1221. + mxsfb_mpu_access(mxsfb, MPU_DATA, MPU_WRITE, 0x05);
  1222. +
  1223. + mxsfb_mpu_access(mxsfb, MPU_CMD, MPU_WRITE, 0xB2);
  1224. + mxsfb_mpu_access(mxsfb, MPU_DATA, MPU_WRITE, 0x00);
  1225. + mxsfb_mpu_access(mxsfb, MPU_DATA, MPU_WRITE, 0x08);
  1226. + mxsfb_mpu_access(mxsfb, MPU_DATA, MPU_WRITE, 0x05);
  1227. +
  1228. + mxsfb_mpu_access(mxsfb, MPU_CMD, MPU_WRITE, 0xB3);
  1229. + mxsfb_mpu_access(mxsfb, MPU_DATA, MPU_WRITE, 0x00);
  1230. + mxsfb_mpu_access(mxsfb, MPU_DATA, MPU_WRITE, 0x08);
  1231. + mxsfb_mpu_access(mxsfb, MPU_DATA, MPU_WRITE, 0x05);
  1232. + mxsfb_mpu_access(mxsfb, MPU_DATA, MPU_WRITE, 0x00);
  1233. + mxsfb_mpu_access(mxsfb, MPU_DATA, MPU_WRITE, 0x08);
  1234. + mxsfb_mpu_access(mxsfb, MPU_DATA, MPU_WRITE, 0x05);
  1235. +
  1236. + /* Power sequence */
  1237. + mxsfb_mpu_access(mxsfb, MPU_CMD, MPU_WRITE, 0xC0);
  1238. + mxsfb_mpu_access(mxsfb, MPU_DATA, MPU_WRITE, 0xA2);
  1239. + mxsfb_mpu_access(mxsfb, MPU_DATA, MPU_WRITE, 0x02);
  1240. + mxsfb_mpu_access(mxsfb, MPU_DATA, MPU_WRITE, 0x84);
  1241. +
  1242. + mxsfb_mpu_access(mxsfb, MPU_CMD, MPU_WRITE, 0xC1);
  1243. + mxsfb_mpu_access(mxsfb, MPU_DATA, MPU_WRITE, 0xC5);
  1244. +
  1245. + mxsfb_mpu_access(mxsfb, MPU_CMD, MPU_WRITE, 0xC2);
  1246. + mxsfb_mpu_access(mxsfb, MPU_DATA, MPU_WRITE, 0x0A);
  1247. + mxsfb_mpu_access(mxsfb, MPU_DATA, MPU_WRITE, 0x00);
  1248. +
  1249. + mxsfb_mpu_access(mxsfb, MPU_CMD, MPU_WRITE, 0xC3);
  1250. + mxsfb_mpu_access(mxsfb, MPU_DATA, MPU_WRITE, 0x8A);
  1251. + mxsfb_mpu_access(mxsfb, MPU_DATA, MPU_WRITE, 0x2A);
  1252. +
  1253. + mxsfb_mpu_access(mxsfb, MPU_CMD, MPU_WRITE, 0xC4);
  1254. + mxsfb_mpu_access(mxsfb, MPU_DATA, MPU_WRITE, 0x8A);
  1255. + mxsfb_mpu_access(mxsfb, MPU_DATA, MPU_WRITE, 0xEE);
  1256. +
  1257. + /* VCOM */
  1258. + mxsfb_mpu_access(mxsfb, MPU_CMD, MPU_WRITE, 0xC5);
  1259. + mxsfb_mpu_access(mxsfb, MPU_DATA, MPU_WRITE, 0x0E);
  1260. +
  1261. + /* Gamma sequence */
  1262. + mxsfb_mpu_access(mxsfb, MPU_CMD, MPU_WRITE, 0xE0);
  1263. + mxsfb_mpu_access(mxsfb, MPU_DATA, MPU_WRITE, 0x12);
  1264. + mxsfb_mpu_access(mxsfb, MPU_DATA, MPU_WRITE, 0x18);
  1265. + mxsfb_mpu_access(mxsfb, MPU_DATA, MPU_WRITE, 0x10);
  1266. + mxsfb_mpu_access(mxsfb, MPU_DATA, MPU_WRITE, 0x18);
  1267. + mxsfb_mpu_access(mxsfb, MPU_DATA, MPU_WRITE, 0x33);
  1268. + mxsfb_mpu_access(mxsfb, MPU_DATA, MPU_WRITE, 0x2C);
  1269. + mxsfb_mpu_access(mxsfb, MPU_DATA, MPU_WRITE, 0x25);
  1270. + mxsfb_mpu_access(mxsfb, MPU_DATA, MPU_WRITE, 0x28);
  1271. + mxsfb_mpu_access(mxsfb, MPU_DATA, MPU_WRITE, 0x28);
  1272. + mxsfb_mpu_access(mxsfb, MPU_DATA, MPU_WRITE, 0x27);
  1273. + mxsfb_mpu_access(mxsfb, MPU_DATA, MPU_WRITE, 0x2F);
  1274. + mxsfb_mpu_access(mxsfb, MPU_DATA, MPU_WRITE, 0x3C);
  1275. + mxsfb_mpu_access(mxsfb, MPU_DATA, MPU_WRITE, 0x00);
  1276. + mxsfb_mpu_access(mxsfb, MPU_DATA, MPU_WRITE, 0x03);
  1277. + mxsfb_mpu_access(mxsfb, MPU_DATA, MPU_WRITE, 0x03);
  1278. + mxsfb_mpu_access(mxsfb, MPU_DATA, MPU_WRITE, 0x10);
  1279. +
  1280. + mxsfb_mpu_access(mxsfb, MPU_CMD, MPU_WRITE, 0xE1);
  1281. + mxsfb_mpu_access(mxsfb, MPU_DATA, MPU_WRITE, 0x12);
  1282. + mxsfb_mpu_access(mxsfb, MPU_DATA, MPU_WRITE, 0x18);
  1283. + mxsfb_mpu_access(mxsfb, MPU_DATA, MPU_WRITE, 0x10);
  1284. + mxsfb_mpu_access(mxsfb, MPU_DATA, MPU_WRITE, 0x18);
  1285. + mxsfb_mpu_access(mxsfb, MPU_DATA, MPU_WRITE, 0x2D);
  1286. + mxsfb_mpu_access(mxsfb, MPU_DATA, MPU_WRITE, 0x28);
  1287. + mxsfb_mpu_access(mxsfb, MPU_DATA, MPU_WRITE, 0x23);
  1288. + mxsfb_mpu_access(mxsfb, MPU_DATA, MPU_WRITE, 0x28);
  1289. + mxsfb_mpu_access(mxsfb, MPU_DATA, MPU_WRITE, 0x28);
  1290. + mxsfb_mpu_access(mxsfb, MPU_DATA, MPU_WRITE, 0x26);
  1291. + mxsfb_mpu_access(mxsfb, MPU_DATA, MPU_WRITE, 0x2F);
  1292. + mxsfb_mpu_access(mxsfb, MPU_DATA, MPU_WRITE, 0x3B);
  1293. + mxsfb_mpu_access(mxsfb, MPU_DATA, MPU_WRITE, 0x00);
  1294. + mxsfb_mpu_access(mxsfb, MPU_DATA, MPU_WRITE, 0x03);
  1295. + mxsfb_mpu_access(mxsfb, MPU_DATA, MPU_WRITE, 0x03);
  1296. + mxsfb_mpu_access(mxsfb, MPU_DATA, MPU_WRITE, 0x10);
  1297. +
  1298. + mxsfb_mpu_access(mxsfb, MPU_CMD, MPU_WRITE, 0x3A);
  1299. + if (mxsfb->mpu_lcd_sigs->panel_bpp == 16)
  1300. + mxsfb_mpu_access(mxsfb, MPU_DATA, MPU_WRITE, 0x55);
  1301. + else
  1302. + mxsfb_mpu_access(mxsfb, MPU_DATA, MPU_WRITE, 0x66); /* 18 bpp */
  1303. +
  1304. + /* Set row address */
  1305. + mxsfb_mpu_access(mxsfb, MPU_CMD, MPU_WRITE, 0x2A);
  1306. + mxsfb_mpu_access(mxsfb, MPU_DATA, MPU_WRITE, 0x00);
  1307. + mxsfb_mpu_access(mxsfb, MPU_DATA, MPU_WRITE, 0x00);
  1308. + mxsfb_mpu_access(mxsfb, MPU_DATA, MPU_WRITE, (((st7735r_lcd_modedb[0].xres - 1) >> 8) & 0xFF));
  1309. + mxsfb_mpu_access(mxsfb, MPU_DATA, MPU_WRITE, ((st7735r_lcd_modedb[0].xres - 1) & 0xFF));
  1310. +
  1311. + /* Set column address */
  1312. + mxsfb_mpu_access(mxsfb, MPU_CMD, MPU_WRITE, 0x2B);
  1313. + mxsfb_mpu_access(mxsfb, MPU_DATA, MPU_WRITE, 0x00);
  1314. + mxsfb_mpu_access(mxsfb, MPU_DATA, MPU_WRITE, 0x00);
  1315. + mxsfb_mpu_access(mxsfb, MPU_DATA, MPU_WRITE, (((st7735r_lcd_modedb[0].yres - 1) >> 8) & 0xFF));
  1316. + mxsfb_mpu_access(mxsfb, MPU_DATA, MPU_WRITE, ((st7735r_lcd_modedb[0].yres - 1) & 0xFF));
  1317. +
  1318. + /* Display on */
  1319. + mxsfb_mpu_access(mxsfb, MPU_CMD, MPU_WRITE, 0x29);
  1320. +
  1321. + /* Memory write */
  1322. + mxsfb_mpu_access(mxsfb, MPU_CMD, MPU_WRITE, 0x2C);
  1323. +
  1324. + return 0;
  1325. +}
  1326. +
  1327. +int mpu_st7735r_lcd_poweroff(struct mxsfb_info * mxsfb)
  1328. +{
  1329. + /* Display off */
  1330. + mxsfb_mpu_access(mxsfb, MPU_CMD, MPU_WRITE, 0x28);
  1331. +
  1332. + /* Sleep in */
  1333. + mxsfb_mpu_access(mxsfb, MPU_CMD, MPU_WRITE, 0x10);
  1334. +
  1335. + return 0;
  1336. +}
  1337. diff --git a/drivers/video/fbdev/mxsfb.c b/drivers/video/fbdev/mxsfb.c
  1338. index 17fe13e4b53b..875577aa9cdd 100644
  1339. --- a/drivers/video/fbdev/mxsfb.c
  1340. +++ b/drivers/video/fbdev/mxsfb.c
  1341. @@ -73,6 +73,12 @@ static struct mpu_match_lcd mpu_lcd_db[] = {
  1342. "ST7789S-QVGA",
  1343. {mpu_st7789s_get_lcd_videomode, mpu_st7789s_lcd_setup, mpu_st7789s_lcd_poweroff}
  1344. },
  1345. +#endif
  1346. +#ifdef CONFIG_FB_MXS_ST7735R_SQUARE
  1347. + {
  1348. + "ST7735R-SQUARE",
  1349. + {mpu_st7735r_get_lcd_videomode, mpu_st7735r_lcd_setup, mpu_st7735r_lcd_poweroff}
  1350. + },
  1351. #endif
  1352. {
  1353. "", {NULL, NULL}
  1354. diff --git a/drivers/video/fbdev/mxsfb.h b/drivers/video/fbdev/mxsfb.h
  1355. index 822d4ebb9cc9..b922cc5fcf00 100644
  1356. --- a/drivers/video/fbdev/mxsfb.h
  1357. +++ b/drivers/video/fbdev/mxsfb.h
  1358. @@ -368,4 +368,11 @@ int mpu_st7789s_lcd_setup(struct mxsfb_info * mxsfb);
  1359. int mpu_st7789s_lcd_poweroff(struct mxsfb_info * mxsfb);
  1360. #endif
  1361.  
  1362. +#ifdef CONFIG_FB_MXS_ST7735R_SQUARE
  1363. +void mpu_st7735r_get_lcd_videomode(struct fb_videomode **mode, int *size,
  1364. + struct mpu_lcd_config **data);
  1365. +int mpu_st7735r_lcd_setup(struct mxsfb_info * mxsfb);
  1366. +int mpu_st7735r_lcd_poweroff(struct mxsfb_info * mxsfb);
  1367. +#endif
  1368. +
  1369. #endif
  1370. --
  1371. 2.19.1
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