fpga clock

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity I2C_Controller is
	Port (
		clk : in STD_LOGIC;
		scl : out STD_LOGIC;
);
end I2C_Controller;

architecture Behavioral of I2C_Controller is
	signal time_counter : integer := 0;
	signal scl_internal : STD_LOGIC := '0';

begin
	process (clk)
	begin
		if rising_edge(clk) then
			if time_counter = 120 then -- scl 100 kHz/ fpga clock is 12MHz
				time_counter <= 0;
				scl_internal <= not scl_internal;
			else
				time_counter <= time_counter + 1;
			end if;
		end if;
	end process;
	scl <= scl_internal;
end architecture Behavioral;