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Apr 4th, 2020
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  1. `timescale 1ns / 1ps
  2.  
  3. module ALU(
  4.     input [3:0] i_OpCode,
  5.  
  6.     input [1:0] i_ForASel,
  7.     input signed [31:0] i_ForA0,
  8.     input signed [31:0] i_ForA1,
  9.     input signed [31:0] i_ForA2,
  10.    
  11.     input [1:0] i_ForBSel,
  12.     input signed [31:0] i_ForB0,
  13.     input signed [31:0] i_ForB1,
  14.     input signed [31:0] i_ForB2,
  15.  
  16.     input i_SrcBSel,
  17.     input signed [31:0] i_SrcB1,
  18.  
  19.     output reg signed[31:0] o_Result,
  20.     output o_Zero
  21.     );
  22.  
  23.     assign o_Zero = (o_Result == 32'b0) ? 1'b1 : 1'b0;
  24.  
  25.     //The various ALU operations
  26.     parameter ALU_ADD   = 4'b0000;
  27.     parameter ALU_SUB   = 4'b1000;
  28.     parameter ALU_AND   = 4'b0111;
  29.     parameter ALU_OR    = 4'b0110;
  30.     parameter ALU_XOR   = 4'b0100;
  31.     parameter ALU_SLL   = 4'b0001;
  32.     parameter ALU_SRL   = 4'b0101;
  33.     parameter ALU_SRA   = 4'b1101;
  34.    
  35.     //Forward muxes
  36.     wire signed[31:0]mux_ForA[2:0] = {i_ForA2, i_ForA1, i_ForA0};
  37.     wire signed[31:0]mux_ForB[2:0] = {i_ForB2, i_ForB1, i_ForB0};
  38.  
  39.     wire signed[31:0]w_SrcA = mux_ForA[i_ForASel];
  40.     wire signed[31:0]w_SrcB0 = mux_ForB[i_ForBSel];
  41.    
  42.     wire signed[31:0]w_SrcB = i_SrcBSel?i_SrcB1:w_SrcB0;
  43.  
  44.     always @(*) begin
  45.         case (i_OpCode)
  46.             ALU_ADD:begin
  47.                 o_Result <= w_SrcA + w_SrcB;
  48.             end
  49.             ALU_SUB:begin
  50.                 o_Result <= w_SrcA -  w_SrcB;
  51.             end  
  52.             ALU_AND:begin
  53.                 o_Result <= w_SrcA &  w_SrcB;
  54.             end  
  55.             ALU_OR:begin
  56.                 o_Result <= w_SrcA |  w_SrcB;
  57.             end
  58.             ALU_XOR:begin
  59.                 o_Result <= w_SrcA ^  w_SrcB;
  60.             end
  61.             ALU_SLL:begin
  62.                 o_Result <= w_SrcA << w_SrcB[4:0];
  63.             end  
  64.             ALU_SRL:begin
  65.                 o_Result <= w_SrcA >> w_SrcB[4:0];
  66.             end  
  67.             ALU_SRA:begin
  68.                 o_Result <= w_SrcA >>> w_SrcB[4:0];
  69.             end
  70.             default:begin
  71.                 o_Result <= 32'b0;
  72.             end  
  73.         endcase
  74.     end
  75.  
  76. endmodule
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