module fifo_arbiter(
    input A,
    input B,
    input C,
    input D,
    input CLK,
    output reg A_take,
    output reg B_take,
    output reg C_take,
    output reg D_take,
    output reg [1:0] ADDR,
    output reg READY
);

reg [3:0] states;
reg [2:0] cycle;

initial begin
    states = 0;
    A_take <= 0;
    B_take <= 0;
    C_take <= 0;
    D_take <= 0;
end

always @(posedge CLK)
begin
        if(A || B || C || D)
        begin
        READY <= 1;
            if(A && ~ states[0])
            begin
                ADDR <= 0;
                states[0] <= 1;
                A_take <= 1;
            end
            else
            begin
                A_take <= 0;
                if(B && ~states[1])
                begin
                    ADDR <= 1;
                    states[1] <= 1;
                    B_take <= 1;
                end
                else
                begin
                    B_take <= 0;
                    if(C && ~states[2])
                    begin
                        ADDR <= 2;
                        states[2] <= 1;
                        C_take <= 1;
                    end
                    else
                    begin
                        C_take <= 0;
                        if(D && ~states[3])
                        begin
                            ADDR <= 3;
                            states[3] <= 1;
                            D_take <= 1;
                        end
                        else
                            D_take <= 0;
                    end
                end
            end

        if(states == {D, C, B, A})
            states <= 0;

        end
        else
        begin
            READY <= 0;
            states <= 0;
            A_take <= 0;
            B_take <= 0;
            C_take <= 0;
            D_take <= 0;
        end
end

endmodule