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  1. frank@xps8900:~/parallella/oh/src/parallella/fpga$ make
  2. make -C parallella_base/ all
  3. make[1]: Entering directory '/home/frank/parallella/oh/src/parallella/fpga/parallella_base'
  4. vivado -mode batch -source run.tcl
  5.  
  6. ****** Vivado v2017.2 (64-bit)
  7. **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017
  8. **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017
  9. ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
  10.  
  11. source run.tcl
  12. # source ./system_params.tcl
  13. ## set design parallella_base
  14. ## set projdir ./
  15. ## set root "../../.."
  16. ## set partname "xc7z020clg400-1"
  17. ## set hdl_files [list \
  18. ## $root/parallella/hdl \
  19. ## $root/common/hdl/ \
  20. ## $root/emesh/hdl \
  21. ## $root/emmu/hdl \
  22. ## $root/axi/hdl \
  23. ## $root/emailbox/hdl \
  24. ## $root/edma/hdl \
  25. ## $root/elink/hdl \
  26. ## ]
  27. ## set ip_files [list \
  28. ## $root/xilibs/ip/fifo_async_104x32.xci \
  29. ## ]
  30. ## set constraints_files []
  31. # source ../../../common/fpga/create_ip.tcl
  32. ## create_project -force $design $projdir -part $partname
  33. ## set_property target_language Verilog [current_project]
  34. ## set_property source_mgmt_mode None [current_project]
  35. ## if {[string equal [get_filesets -quiet sources_1] ""]} {
  36. ## create_fileset -srcset sources_1
  37. ## }
  38. ## add_files -norecurse -fileset [get_filesets sources_1] $hdl_files
  39. ## set_property top $design [get_filesets sources_1]
  40. ## if {[string equal [get_filesets -quiet constraints_1] ""]} {
  41. ## create_fileset -constrset constraints_1
  42. ## }
  43. ## if {[llength $constraints_files] != 0} {
  44. ## add_files -norecurse -fileset [get_filesets constraints_1] $constraints_files
  45. ## }
  46. ## if {[llength $ip_files] != 0} {
  47. ## file delete -force ip_tmp
  48. ## file mkdir ip_tmp
  49. ##
  50. ## #Set mode for IP
  51. ## foreach file $ip_files {
  52. ## set file_name [file tail $file]
  53. ## set ip_name [file rootname [file tail $file]]
  54. ## set local_file ip_tmp/$file_name
  55. ##
  56. ## # Create local copy
  57. ## file copy $file ip_tmp
  58. ## add_files -norecurse -fileset [get_filesets sources_1] $local_file
  59. ##
  60. ## # Upgrade if needed
  61. ## set locked [get_property IS_LOCKED [get_ips $ip_name]]
  62. ## set upgrade [get_property UPGRADE_VERSIONS [get_ips $ip_name]]
  63. ## if {$upgrade != "" && $locked} {
  64. ## upgrade_ip [get_ips $ip_name]
  65. ## }
  66. ##
  67. ## #TODO: is this needed?
  68. ## set local_file_obj [get_files -of_objects [get_filesets sources_1] $local_file]
  69. ## set_property "synth_checkpoint_mode" "Singular" $local_file_obj
  70. ## }
  71. ##
  72. ##
  73. ## }
  74. INFO: [IP_Flow 19-234] Refreshing IP repositories
  75. INFO: [IP_Flow 19-1704] No user IP repositories specified
  76. INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2017.2/data/ip'.
  77. WARNING: [IP_Flow 19-2162] IP 'fifo_async_104x32' is locked:
  78. * IP definition 'FIFO Generator (13.1)' for IP 'fifo_async_104x32' (customized with software release 2016.4) has a different revision in the IP Catalog.
  79. * Current project part 'xc7z020clg400-1' and the part 'xczu9eg-ffvb1156-2-i-es2' used to customize the IP 'fifo_async_104x32' do not match.
  80. Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information.
  81. Upgrading 'fifo_async_104x32'
  82. INFO: [IP_Flow 19-3420] Updated fifo_async_104x32 to use current project options
  83. INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'fifo_async_104x32'...
  84. ## ipx::package_project -import_files -force -root_dir $projdir
  85. WARNING: [Ipptcl 7-1467] The compile order has been set manually. This prevents the packager from updating it if necessary. If errors related to compile order occur, try enabling automatic reordering, or calling package_project with the -force_update_compile_order option
  86. WARNING: [IP_Flow 19-3899] Cannot get the environment domain name variable for the component vendor name. Setting the vendor name to 'user.org'.
  87. CRITICAL WARNING: [HDL 9-870] Macro <CFG_ASIC> is not defined. [/home/frank/parallella/oh/src/parallella/fpga/parallella_base/src/oh_lat0.v:15]
  88. CRITICAL WARNING: [HDL 9-806] Syntax error near ";". [/home/frank/parallella/oh/src/parallella/fpga/parallella_base/src/oh_lat0.v:15]
  89. CRITICAL WARNING: [HDL 9-806] Syntax error near "|". [/home/frank/parallella/oh/src/parallella/fpga/parallella_base/src/oh_mux.v:24]
  90. CRITICAL WARNING: [HDL 9-806] Syntax error near "&". [/home/frank/parallella/oh/src/parallella/fpga/parallella_base/src/oh_mux.v:24]
  91. CRITICAL WARNING: [HDL 9-806] Syntax error near ";". [/home/frank/parallella/oh/src/parallella/fpga/parallella_base/src/oh_mux.v:24]
  92. CRITICAL WARNING: [HDL 9-806] Syntax error near ";". [/home/frank/parallella/oh/src/parallella/fpga/parallella_base/src/oh_memory_sp.v:36]
  93. CRITICAL WARNING: [HDL 9-806] Syntax error near ";". [/home/frank/parallella/oh/src/parallella/fpga/parallella_base/src/oh_buffer.v:14]
  94. CRITICAL WARNING: [HDL 9-806] Syntax error near ";". [/home/frank/parallella/oh/src/parallella/fpga/parallella_base/src/oh_clockgate.v:15]
  95. CRITICAL WARNING: [HDL 9-806] Syntax error near ";". [/home/frank/parallella/oh/src/parallella/fpga/parallella_base/src/oh_lat1.v:15]
  96. CRITICAL WARNING: [HDL 9-806] Syntax error near ";". [/home/frank/parallella/oh/src/parallella/fpga/parallella_base/src/oh_dsync.v:18]
  97. CRITICAL WARNING: [HDL 9-806] Syntax error near ";". [/home/frank/parallella/oh/src/parallella/fpga/parallella_base/src/oh_memory_dp.v:36]
  98. CRITICAL WARNING: [HDL 9-806] Syntax error near ";". [/home/frank/parallella/oh/src/parallella/fpga/parallella_base/src/oh_pwr_gate.v:14]
  99. CRITICAL WARNING: [HDL 9-806] Syntax error near ";". [/home/frank/parallella/oh/src/parallella/fpga/parallella_base/src/oh_delay.v:16]
  100. CRITICAL WARNING: [HDL 9-806] Syntax error near ";". [/home/frank/parallella/oh/src/parallella/fpga/parallella_base/src/oh_clockor.v:14]
  101. CRITICAL WARNING: [HDL 9-806] Syntax error near ";". [/home/frank/parallella/oh/src/parallella/fpga/parallella_base/src/oh_clockmux.v:15]
  102. CRITICAL WARNING: [HDL 9-806] Syntax error near ";". [/home/frank/parallella/oh/src/parallella/fpga/parallella_base/src/oh_csa42.v:20]
  103. CRITICAL WARNING: [HDL 9-806] Syntax error near ";". [/home/frank/parallella/oh/src/parallella/fpga/parallella_base/src/oh_pwr_isohi.v:16]
  104. CRITICAL WARNING: [HDL 9-806] Syntax error near ";". [/home/frank/parallella/oh/src/parallella/fpga/parallella_base/src/oh_reg0.v:16]
  105. CRITICAL WARNING: [HDL 9-806] Syntax error near ";". [/home/frank/parallella/oh/src/parallella/fpga/parallella_base/src/oh_pwr_isolo.v:16]
  106. CRITICAL WARNING: [HDL 9-806] Syntax error near ";". [/home/frank/parallella/oh/src/parallella/fpga/parallella_base/src/oh_csa32.v:17]
  107. CRITICAL WARNING: [HDL 9-806] Syntax error near ";". [/home/frank/parallella/oh/src/parallella/fpga/parallella_base/src/oh_reg1.v:16]
  108. CRITICAL WARNING: [HDL 9-806] Syntax error near ";". [/home/frank/parallella/oh/src/parallella/fpga/parallella_base/src/oh_rsync.v:16]
  109. INFO: [IP_Flow 19-1842] HDL Parser: Found include file "src/emailbox_regmap.vh" from the top-level HDL file.
  110. INFO: [IP_Flow 19-1842] HDL Parser: Found include file "src/edma_regmap.vh" from the top-level HDL file.
  111. INFO: [IP_Flow 19-1842] HDL Parser: Found include file "src/elink_regmap.vh" from the top-level HDL file.
  112. INFO: [IP_Flow 19-1842] HDL Parser: Found include file "src/elink_constants.vh" from the top-level HDL file.
  113. INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository).
  114. INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository).
  115. INFO: [IP_Flow 19-4753] Inferred signal 'reset' from port 'm_axi_aresetn' as interface 'm_axi_aresetn'.
  116. INFO: [IP_Flow 19-4728] Bus Interface 'm_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
  117. INFO: [IP_Flow 19-4753] Inferred signal 'reset' from port 's_axi_aresetn' as interface 's_axi_aresetn'.
  118. INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
  119. INFO: [IP_Flow 19-4753] Inferred signal 'interrupt' from port 'mailbox_irq' as interface 'mailbox_irq'.
  120. INFO: [IP_Flow 19-4728] Bus Interface 'mailbox_irq': Added interface parameter 'SENSITIVITY' with value 'LEVEL_HIGH'.
  121. INFO: [IP_Flow 19-4753] Inferred signal 'clock' from port 'sys_clk' as interface 'sys_clk'.
  122. ## ipx::remove_memory_map {s_axi} [ipx::current_core]
  123. ## ipx::add_memory_map {s_axi} [ipx::current_core]
  124. ## ipx::associate_bus_interfaces -busif s_axi -clock sys_clk [ipx::current_core]
  125. INFO: [IP_Flow 19-4728] Bus Interface 'sys_clk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'.
  126. ## ipx::associate_bus_interfaces -busif m_axi -clock sys_clk [ipx::current_core]
  127. WARNING: command 'get_bus_interface' will be removed in the 2015.3 release, use 'get_bus_interfaces' instead
  128. ## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interface s_axi [ipx::current_core]]
  129. WARNING: command 'get_memory_map' will be removed in the 2015.3 release, use 'get_memory_maps' instead
  130. ## ipx::add_address_block {axi_lite} [ipx::get_memory_map s_axi [ipx::current_core]]
  131. WARNING: command 'get_memory_map' will be removed in the 2015.3 release, use 'get_memory_maps' instead
  132. WARNING: command 'get_address_block' will be removed in the 2015.3 release, use 'get_address_blocks' instead
  133. ## set_property range {65536} [ipx::get_address_block axi_lite \
  134. ## [ipx::get_memory_map s_axi [ipx::current_core]]]
  135. ## set_property vendor {www.parallella.org} [ipx::current_core]
  136. ## set_property library {user} [ipx::current_core]
  137. ## set_property taxonomy {{/AXI_Infrastructure}} [ipx::current_core]
  138. ## set_property vendor_display_name {ADAPTEVA} [ipx::current_core]
  139. ## set_property company_url {www.parallella.org} [ipx::current_core]
  140. ## set_property supported_families { \
  141. ## {virtex7} {Production} \
  142. ## {qvirtex7} {Production} \
  143. ## {kintex7} {Production} \
  144. ## {kintex7l} {Production} \
  145. ## {qkintex7} {Production} \
  146. ## {qkintex7l} {Production} \
  147. ## {artix7} {Production} \
  148. ## {artix7l} {Production} \
  149. ## {aartix7} {Production} \
  150. ## {qartix7} {Production} \
  151. ## {zynq} {Production} \
  152. ## {qzynq} {Production} \
  153. ## {azynq} {Production} \
  154. ## {zynquplus} {Production} \
  155. ## } [ipx::current_core]
  156. WARNING: [IP_Flow 19-4623] Unrecognized family virtex7. Please verify spelling and reissue command to set the supported files.
  157. WARNING: [IP_Flow 19-4623] Unrecognized family qvirtex7. Please verify spelling and reissue command to set the supported files.
  158. WARNING: [IP_Flow 19-4623] Unrecognized family qkintex7. Please verify spelling and reissue command to set the supported files.
  159. WARNING: [IP_Flow 19-4623] Unrecognized family qkintex7l. Please verify spelling and reissue command to set the supported files.
  160. WARNING: [IP_Flow 19-4623] Unrecognized family qartix7. Please verify spelling and reissue command to set the supported files.
  161. WARNING: [IP_Flow 19-4623] Unrecognized family qzynq. Please verify spelling and reissue command to set the supported files.
  162. ## ipx::archive_core [concat $design.zip] [ipx::current_core]
  163. ## exit
  164. INFO: [Common 17-206] Exiting Vivado at Tue Aug 8 01:36:24 2017...
  165. make[1]: Leaving directory '/home/frank/parallella/oh/src/parallella/fpga/parallella_base'
  166. make -C headless_e16_z7010/ all
  167. make[1]: Entering directory '/home/frank/parallella/oh/src/parallella/fpga/headless_e16_z7010'
  168. rm -f system_wrapper.bit.bin bit2bin.bin
  169. vivado -mode batch -source run.tcl
  170.  
  171. ****** Vivado v2017.2 (64-bit)
  172. **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017
  173. **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017
  174. ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
  175.  
  176. source run.tcl
  177. # source ./system_params.tcl
  178. ## set design system
  179. ## set projdir ./
  180. ## set partname "xc7z010clg400-1"
  181. ## set ip_repos [list "../parallella_base"]
  182. ## set hdl_files []
  183. ## set constraints_files [list \
  184. ## ../parallella_timing.xdc \
  185. ## ../parallella_io.xdc \
  186. ## ]
  187. ## set oh_synthesis_options "-verilog_define CFG_ASIC=0"
  188. # source ../../../common/fpga/system_init.tcl
  189. ## create_project -force $design $projdir -part $partname
  190. ## set_property target_language Verilog [current_project]
  191. ## if {[info exists board_part]} {
  192. ## set_property board_part $board_part [current_project]
  193. ## }
  194. ## set report_dir $projdir/reports
  195. ## set results_dir $projdir/results
  196. ## if ![file exists $report_dir] {file mkdir $report_dir}
  197. ## if ![file exists $results_dir] {file mkdir $results_dir}
  198. ## set other_repos [get_property ip_repo_paths [current_project]]
  199. ## set_property ip_repo_paths "$ip_repos $other_repos" [current_project]
  200. ## update_ip_catalog
  201. INFO: [IP_Flow 19-234] Refreshing IP repositories
  202. INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/frank/parallella/oh/src/parallella/fpga/parallella_base'.
  203. INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2017.2/data/ip'.
  204. ## create_bd_design "system"
  205. Wrote : </home/frank/parallella/oh/src/parallella/fpga/headless_e16_z7010/system.srcs/sources_1/bd/system/system.bd>
  206. ## source $projdir/system_bd.tcl
  207. ### set scripts_vivado_version 2015.2
  208. ### set current_vivado_version [version -short]
  209. ### if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
  210. ### puts ""
  211. ### puts "ERROR: This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."
  212. ###
  213. ### return 1
  214. ### }
  215.  
  216. ERROR: This script was generated using Vivado <2015.2> and is being run in <2017.2> of Vivado. Please run the script in Vivado <2015.2> then open the design in Vivado <2017.2>. Upgrade the design by running "Tools => Report => Report IP Status...", then run write_bd_tcl to create an updated script.
  217. ## make_wrapper -files [get_files $projdir/${design}.srcs/sources_1/bd/system/system.bd] -top
  218. Wrote : </home/frank/parallella/oh/src/parallella/fpga/headless_e16_z7010/system.srcs/sources_1/bd/system/system.bd>
  219. Verilog Output written to : /home/frank/parallella/oh/src/parallella/fpga/headless_e16_z7010/system.srcs/sources_1/bd/system/hdl/system.v
  220. Verilog Output written to : /home/frank/parallella/oh/src/parallella/fpga/headless_e16_z7010/system.srcs/sources_1/bd/system/hdl/system_wrapper.v
  221. ## if {[string equal [get_filesets -quiet sources_1] ""]} {
  222. ## create_fileset -srcset sources_1
  223. ## }
  224. ## set top_wrapper $projdir/${design}.srcs/sources_1/bd/system/hdl/system_wrapper.v
  225. ## add_files -norecurse -fileset [get_filesets sources_1] $top_wrapper
  226. ## if {[llength $hdl_files] != 0} {
  227. ## add_files -norecurse -fileset [get_filesets sources_1] $hdl_files
  228. ## }
  229. ## if {[string equal [get_filesets -quiet constrs_1] ""]} {
  230. ## create_fileset -constrset constrs_1
  231. ## }
  232. ## if {[llength $constraints_files] != 0} {
  233. ## add_files -norecurse -fileset [get_filesets constrs_1] $constraints_files
  234. ## }
  235. # source ../../../common/fpga/system_build.tcl
  236. ## if {![info exists design]} {
  237. ## set design system
  238. ## puts "INFO: Setting design name to '${design}'"
  239. ## }
  240. ## validate_bd_design
  241. INFO: [BD 5-320] Validate design is not run, since the design is already validated.
  242. ## write_bd_tcl -force ./${design}_bd.tcl
  243. INFO: [BD 5-148] Tcl file written out </home/frank/parallella/oh/src/parallella/fpga/headless_e16_z7010/system_bd.tcl>.
  244.  
  245. ## make_wrapper -files [get_files $projdir/${design}.srcs/sources_1/bd/${design}/${design}.bd] -top
  246. INFO: [BD 41-1662] The design 'system.bd' is already validated. Therefore parameter propagation will not be re-run.
  247. Verilog Output written to : /home/frank/parallella/oh/src/parallella/fpga/headless_e16_z7010/system.srcs/sources_1/bd/system/hdl/system.v
  248. Verilog Output written to : /home/frank/parallella/oh/src/parallella/fpga/headless_e16_z7010/system.srcs/sources_1/bd/system/hdl/system_wrapper.v
  249. ## remove_files -fileset sources_1 $projdir/${design}.srcs/sources_1/bd/${design}/hdl/${design}_wrapper.v
  250. ## add_files -fileset sources_1 -norecurse $projdir/${design}.srcs/sources_1/bd/${design}/hdl/${design}_wrapper.v
  251. ## if {[info exists oh_synthesis_options]} {
  252. ## puts "INFO: Synthesis with following options: $oh_synthesis_options"
  253. ## set_property -name {STEPS.SYNTH_DESIGN.ARGS.MORE OPTIONS} -value $oh_synthesis_options -objects [get_runs synth_1]
  254. ## }
  255. INFO: Synthesis with following options: -verilog_define CFG_ASIC=0
  256. ## if {[info exists oh_verilog_define]} {
  257. ## puts "INFO: Adding following verilog defines to fileset: ${oh_verilog_define}"
  258. ## set_property verilog_define ${oh_verilog_define} [current_fileset]
  259. ## }
  260. ## launch_runs synth_1
  261. INFO: [BD 41-1662] The design 'system.bd' is already validated. Therefore parameter propagation will not be re-run.
  262. Verilog Output written to : /home/frank/parallella/oh/src/parallella/fpga/headless_e16_z7010/system.srcs/sources_1/bd/system/hdl/system.v
  263. Verilog Output written to : /home/frank/parallella/oh/src/parallella/fpga/headless_e16_z7010/system.srcs/sources_1/bd/system/hdl/system_wrapper.v
  264. Exporting to file /home/frank/parallella/oh/src/parallella/fpga/headless_e16_z7010/system.srcs/sources_1/bd/system/hw_handoff/system.hwh
  265. Generated Block Design Tcl file /home/frank/parallella/oh/src/parallella/fpga/headless_e16_z7010/system.srcs/sources_1/bd/system/hw_handoff/system_bd.tcl
  266. Generated Hardware Definition File /home/frank/parallella/oh/src/parallella/fpga/headless_e16_z7010/system.srcs/sources_1/bd/system/hdl/system.hwdef
  267. [Tue Aug 8 01:36:34 2017] Launched synth_1...
  268. Run output will be captured here: /home/frank/parallella/oh/src/parallella/fpga/headless_e16_z7010/system.runs/synth_1/runme.log
  269. ## wait_on_run synth_1
  270. [Tue Aug 8 01:36:34 2017] Waiting for synth_1 to finish...
  271.  
  272. *** Running vivado
  273. with args -log system_wrapper.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source system_wrapper.tcl
  274.  
  275.  
  276. ****** Vivado v2017.2 (64-bit)
  277. **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017
  278. **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017
  279. ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
  280.  
  281. source system_wrapper.tcl -notrace
  282. Command: synth_design -top system_wrapper -part xc7z010clg400-1 -verilog_define CFG_ASIC=0
  283. Starting synth_design
  284. Attempting to get a license for feature 'Synthesis' and/or device 'xc7z010-clg400'
  285. INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z010-clg400'
  286. INFO: Launching helper process for spawning children vivado processes
  287. INFO: Helper process launched with PID 8302
  288. ---------------------------------------------------------------------------------
  289. Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 1142.168 ; gain = 45.996 ; free physical = 222 ; free virtual = 11016
  290. ---------------------------------------------------------------------------------
  291. INFO: [Synth 8-638] synthesizing module 'system_wrapper' [/home/frank/parallella/oh/src/parallella/fpga/headless_e16_z7010/system.srcs/sources_1/bd/system/hdl/system_wrapper.v:12]
  292. INFO: [Synth 8-638] synthesizing module 'system' [/home/frank/parallella/oh/src/parallella/fpga/headless_e16_z7010/system.srcs/sources_1/bd/system/hdl/system.v:13]
  293. INFO: [Synth 8-256] done synthesizing module 'system' (1#1) [/home/frank/parallella/oh/src/parallella/fpga/headless_e16_z7010/system.srcs/sources_1/bd/system/hdl/system.v:13]
  294. WARNING: [Synth 8-115] binding instance 'system_i' in module 'system_wrapper' to reference 'system' which has no pins
  295. INFO: [Synth 8-256] done synthesizing module 'system_wrapper' (2#1) [/home/frank/parallella/oh/src/parallella/fpga/headless_e16_z7010/system.srcs/sources_1/bd/system/hdl/system_wrapper.v:12]
  296. ---------------------------------------------------------------------------------
  297. Finished RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 1183.676 ; gain = 87.504 ; free physical = 300 ; free virtual = 11029
  298. ---------------------------------------------------------------------------------
  299.  
  300. Report Check Netlist:
  301. +------+------------------+-------+---------+-------+------------------+
  302. | |Item |Errors |Warnings |Status |Description |
  303. +------+------------------+-------+---------+-------+------------------+
  304. |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
  305. +------+------------------+-------+---------+-------+------------------+
  306. ---------------------------------------------------------------------------------
  307. Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1183.676 ; gain = 87.504 ; free physical = 300 ; free virtual = 11029
  308. ---------------------------------------------------------------------------------
  309. INFO: [Device 21-403] Loading part xc7z010clg400-1
  310. INFO: [Project 1-570] Preparing netlist for logic optimization
  311.  
  312. Processing XDC Constraints
  313. Initializing timing engine
  314. Parsing XDC File [/home/frank/parallella/oh/src/parallella/fpga/parallella_timing.xdc]
  315. WARNING: [Vivado 12-584] No ports matched 'rxi_lclk_p'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_timing.xdc:1]
  316. WARNING: [Vivado 12-2489] -period contains time 3.333333 which will be rounded to 3.333 to ensure it is an integer multiple of 1 picosecond [/home/frank/parallella/oh/src/parallella/fpga/parallella_timing.xdc:1]
  317. WARNING: [Vivado 12-2489] -waveform contains time 1.666667 which will be rounded to 1.667 to ensure it is an integer multiple of 1 picosecond [/home/frank/parallella/oh/src/parallella/fpga/parallella_timing.xdc:1]
  318. Finished Parsing XDC File [/home/frank/parallella/oh/src/parallella/fpga/parallella_timing.xdc]
  319. WARNING: [Project 1-498] One or more constraints failed evaluation while reading constraint file [/home/frank/parallella/oh/src/parallella/fpga/parallella_timing.xdc] and the design contains unresolved black boxes. These constraints will be read post-synthesis (as long as their source constraint file is marked as used_in_implementation) and should be applied correctly then. You should review the constraints listed in the file [.Xil/system_wrapper_propImpl.xdc] and check the run log file to verify that these constraints were correctly applied.
  320. Parsing XDC File [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc]
  321. WARNING: [Vivado 12-584] No ports matched 'hdmi_*'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:11]
  322. WARNING: [Vivado 12-584] No ports matched 'hdmi_d[8]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:12]
  323. WARNING: [Vivado 12-584] No ports matched 'hdmi_d[9]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:13]
  324. WARNING: [Vivado 12-584] No ports matched 'hdmi_d[10]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:14]
  325. WARNING: [Vivado 12-584] No ports matched 'hdmi_d[11]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:15]
  326. WARNING: [Vivado 12-584] No ports matched 'hdmi_d[12]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:16]
  327. WARNING: [Vivado 12-584] No ports matched 'hdmi_d[13]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:17]
  328. WARNING: [Vivado 12-584] No ports matched 'hdmi_d[14]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:18]
  329. WARNING: [Vivado 12-584] No ports matched 'hdmi_d[15]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:19]
  330. WARNING: [Vivado 12-584] No ports matched 'hdmi_d[16]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:20]
  331. WARNING: [Vivado 12-584] No ports matched 'hdmi_d[17]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:21]
  332. WARNING: [Vivado 12-584] No ports matched 'hdmi_d[18]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:22]
  333. WARNING: [Vivado 12-584] No ports matched 'hdmi_d[19]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:23]
  334. WARNING: [Vivado 12-584] No ports matched 'hdmi_d[20]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:24]
  335. WARNING: [Vivado 12-584] No ports matched 'hdmi_d[21]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:25]
  336. WARNING: [Vivado 12-584] No ports matched 'hdmi_d[22]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:26]
  337. WARNING: [Vivado 12-584] No ports matched 'hdmi_d[23]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:27]
  338. WARNING: [Vivado 12-584] No ports matched 'hdmi_clk'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:28]
  339. WARNING: [Vivado 12-584] No ports matched 'hdmi_vsync'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:29]
  340. WARNING: [Vivado 12-584] No ports matched 'hdmi_hsync'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:30]
  341. WARNING: [Vivado 12-584] No ports matched 'hdmi_de'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:31]
  342. WARNING: [Vivado 12-584] No ports matched 'hdmi_spdif'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:32]
  343. WARNING: [Vivado 12-584] No ports matched 'hdmi_int'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:33]
  344. WARNING: [Vivado 12-584] No ports matched 'i2c_*'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:38]
  345. WARNING: [Vivado 12-584] No ports matched 'i2c_scl'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:39]
  346. WARNING: [Vivado 12-584] No ports matched 'i2c_sda'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:40]
  347. WARNING: [Vivado 12-584] No ports matched 'chip_nreset'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:45]
  348. WARNING: [Vivado 12-584] No ports matched 'chip_nreset'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:46]
  349. WARNING: [Vivado 12-584] No ports matched 'cclk*'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:51]
  350. WARNING: [Vivado 12-584] No ports matched 'cclk_n'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:52]
  351. WARNING: [Vivado 12-584] No ports matched 'txo*'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:57]
  352. WARNING: [Vivado 12-584] No ports matched 'txi*'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:58]
  353. WARNING: [Vivado 12-584] No ports matched 'txo_lclk_n'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:59]
  354. WARNING: [Vivado 12-584] No ports matched 'txo_data_n[0]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:60]
  355. WARNING: [Vivado 12-584] No ports matched 'txo_data_n[1]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:61]
  356. WARNING: [Vivado 12-584] No ports matched 'txo_data_n[2]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:62]
  357. WARNING: [Vivado 12-584] No ports matched 'txo_data_n[3]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:63]
  358. WARNING: [Vivado 12-584] No ports matched 'txo_data_n[4]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:64]
  359. WARNING: [Vivado 12-584] No ports matched 'txo_data_n[5]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:65]
  360. WARNING: [Vivado 12-584] No ports matched 'txo_data_n[6]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:66]
  361. WARNING: [Vivado 12-584] No ports matched 'txo_data_n[7]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:67]
  362. WARNING: [Vivado 12-584] No ports matched 'txo_frame_n'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:68]
  363. WARNING: [Vivado 12-584] No ports matched 'txi_wr_wait_n'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:69]
  364. WARNING: [Vivado 12-584] No ports matched 'txi_rd_wait_*'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:74]
  365. WARNING: [Vivado 12-584] No ports matched 'txi_rd_wait_p'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:75]
  366. WARNING: [Vivado 12-584] No ports matched 'rx*'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:81]
  367. WARNING: [Vivado 12-584] No ports matched 'rxi_lclk_n'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:82]
  368. WARNING: [Vivado 12-584] No ports matched 'rxi_data_n[0]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:83]
  369. WARNING: [Vivado 12-584] No ports matched 'rxi_data_n[1]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:84]
  370. WARNING: [Vivado 12-584] No ports matched 'rxi_data_n[2]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:85]
  371. WARNING: [Vivado 12-584] No ports matched 'rxi_data_n[3]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:86]
  372. WARNING: [Vivado 12-584] No ports matched 'rxi_data_n[4]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:87]
  373. WARNING: [Vivado 12-584] No ports matched 'rxi_data_n[5]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:88]
  374. WARNING: [Vivado 12-584] No ports matched 'rxi_data_n[6]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:89]
  375. WARNING: [Vivado 12-584] No ports matched 'rxi_data_n[7]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:90]
  376. WARNING: [Vivado 12-584] No ports matched 'rxi_frame_n'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:91]
  377. WARNING: [Vivado 12-584] No ports matched 'rxo_rd_wait_n'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:92]
  378. WARNING: [Vivado 12-584] No ports matched 'rxo_wr_wait_n'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:93]
  379. WARNING: [Vivado 12-584] No ports matched 'gpio*'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:99]
  380. WARNING: [Vivado 12-584] No ports matched 'gpio_p[0]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:100]
  381. WARNING: [Vivado 12-584] No ports matched 'gpio_n[0]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:101]
  382. WARNING: [Vivado 12-584] No ports matched 'gpio_p[1]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:102]
  383. WARNING: [Vivado 12-584] No ports matched 'gpio_n[1]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:103]
  384. WARNING: [Vivado 12-584] No ports matched 'gpio_p[2]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:104]
  385. WARNING: [Vivado 12-584] No ports matched 'gpio_n[2]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:105]
  386. WARNING: [Vivado 12-584] No ports matched 'gpio_p[3]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:106]
  387. WARNING: [Vivado 12-584] No ports matched 'gpio_n[3]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:107]
  388. WARNING: [Vivado 12-584] No ports matched 'gpio_p[4]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:108]
  389. WARNING: [Vivado 12-584] No ports matched 'gpio_n[4]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:109]
  390. WARNING: [Vivado 12-584] No ports matched 'gpio_p[5]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:110]
  391. WARNING: [Vivado 12-584] No ports matched 'gpio_n[5]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:111]
  392. WARNING: [Vivado 12-584] No ports matched 'gpio_p[6]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:112]
  393. WARNING: [Vivado 12-584] No ports matched 'gpio_n[6]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:113]
  394. WARNING: [Vivado 12-584] No ports matched 'gpio_p[7]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:114]
  395. WARNING: [Vivado 12-584] No ports matched 'gpio_n[7]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:115]
  396. WARNING: [Vivado 12-584] No ports matched 'gpio_p[8]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:116]
  397. WARNING: [Vivado 12-584] No ports matched 'gpio_n[8]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:117]
  398. WARNING: [Vivado 12-584] No ports matched 'gpio_p[9]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:118]
  399. WARNING: [Vivado 12-584] No ports matched 'gpio_n[9]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:119]
  400. WARNING: [Vivado 12-584] No ports matched 'gpio_p[10]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:120]
  401. WARNING: [Vivado 12-584] No ports matched 'gpio_n[10]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:121]
  402. WARNING: [Vivado 12-584] No ports matched 'gpio_p[11]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:122]
  403. WARNING: [Vivado 12-584] No ports matched 'gpio_n[11]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:123]
  404. Finished Parsing XDC File [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc]
  405. WARNING: [Project 1-498] One or more constraints failed evaluation while reading constraint file [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc] and the design contains unresolved black boxes. These constraints will be read post-synthesis (as long as their source constraint file is marked as used_in_implementation) and should be applied correctly then. You should review the constraints listed in the file [.Xil/system_wrapper_propImpl.xdc] and check the run log file to verify that these constraints were correctly applied.
  406. Parsing XDC File [/home/frank/parallella/oh/src/parallella/fpga/headless_e16_z7010/system.runs/synth_1/dont_touch.xdc]
  407. Finished Parsing XDC File [/home/frank/parallella/oh/src/parallella/fpga/headless_e16_z7010/system.runs/synth_1/dont_touch.xdc]
  408. Completed Processing XDC Constraints
  409.  
  410. INFO: [Project 1-111] Unisim Transformation Summary:
  411. No Unisim elements were transformed.
  412.  
  413. Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1437.918 ; gain = 0.000 ; free physical = 233 ; free virtual = 10808
  414. ---------------------------------------------------------------------------------
  415. Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 1437.918 ; gain = 341.746 ; free physical = 308 ; free virtual = 10877
  416. ---------------------------------------------------------------------------------
  417. ---------------------------------------------------------------------------------
  418. Start Loading Part and Timing Information
  419. ---------------------------------------------------------------------------------
  420. Loading part: xc7z010clg400-1
  421. ---------------------------------------------------------------------------------
  422. Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 1437.918 ; gain = 341.746 ; free physical = 308 ; free virtual = 10878
  423. ---------------------------------------------------------------------------------
  424. ---------------------------------------------------------------------------------
  425. Start Applying 'set_property' XDC Constraints
  426. ---------------------------------------------------------------------------------
  427. Applied set_property DONT_TOUCH = true for system_i. (constraint file auto generated constraint, line ).
  428. ---------------------------------------------------------------------------------
  429. Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 1437.918 ; gain = 341.746 ; free physical = 310 ; free virtual = 10880
  430. ---------------------------------------------------------------------------------
  431. WARNING: [Synth 8-115] binding instance 'system_i' in module 'system_wrapper' to reference 'system' which has no pins
  432. ---------------------------------------------------------------------------------
  433. Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 1437.918 ; gain = 341.746 ; free physical = 310 ; free virtual = 10880
  434. ---------------------------------------------------------------------------------
  435.  
  436. Report RTL Partitions:
  437. +-+--------------+------------+----------+
  438. | |RTL Partition |Replication |Instances |
  439. +-+--------------+------------+----------+
  440. +-+--------------+------------+----------+
  441. ---------------------------------------------------------------------------------
  442. Start RTL Component Statistics
  443. ---------------------------------------------------------------------------------
  444. Detailed RTL Component Info :
  445. ---------------------------------------------------------------------------------
  446. Finished RTL Component Statistics
  447. ---------------------------------------------------------------------------------
  448. ---------------------------------------------------------------------------------
  449. Start RTL Hierarchical Component Statistics
  450. ---------------------------------------------------------------------------------
  451. Hierarchical RTL Component report
  452. ---------------------------------------------------------------------------------
  453. Finished RTL Hierarchical Component Statistics
  454. ---------------------------------------------------------------------------------
  455. ---------------------------------------------------------------------------------
  456. Start Part Resource Summary
  457. ---------------------------------------------------------------------------------
  458. Part Resources:
  459. DSPs: 80 (col length:40)
  460. BRAMs: 120 (col length: RAMB18 40 RAMB36 20)
  461. ---------------------------------------------------------------------------------
  462. Finished Part Resource Summary
  463. ---------------------------------------------------------------------------------
  464. ---------------------------------------------------------------------------------
  465. Start Cross Boundary and Area Optimization
  466. ---------------------------------------------------------------------------------
  467. ---------------------------------------------------------------------------------
  468. Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 1437.918 ; gain = 341.746 ; free physical = 310 ; free virtual = 10880
  469. ---------------------------------------------------------------------------------
  470.  
  471. Report RTL Partitions:
  472. +-+--------------+------------+----------+
  473. | |RTL Partition |Replication |Instances |
  474. +-+--------------+------------+----------+
  475. +-+--------------+------------+----------+
  476. ---------------------------------------------------------------------------------
  477. Start Applying XDC Timing Constraints
  478. ---------------------------------------------------------------------------------
  479. ---------------------------------------------------------------------------------
  480. Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1453.906 ; gain = 357.734 ; free physical = 218 ; free virtual = 10754
  481. ---------------------------------------------------------------------------------
  482. ---------------------------------------------------------------------------------
  483. Start Timing Optimization
  484. ---------------------------------------------------------------------------------
  485. ---------------------------------------------------------------------------------
  486. Finished Timing Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1453.906 ; gain = 357.734 ; free physical = 218 ; free virtual = 10754
  487. ---------------------------------------------------------------------------------
  488.  
  489. Report RTL Partitions:
  490. +-+--------------+------------+----------+
  491. | |RTL Partition |Replication |Instances |
  492. +-+--------------+------------+----------+
  493. +-+--------------+------------+----------+
  494. ---------------------------------------------------------------------------------
  495. Start Technology Mapping
  496. ---------------------------------------------------------------------------------
  497. ---------------------------------------------------------------------------------
  498. Finished Technology Mapping : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1462.918 ; gain = 366.746 ; free physical = 232 ; free virtual = 10753
  499. ---------------------------------------------------------------------------------
  500.  
  501. Report RTL Partitions:
  502. +-+--------------+------------+----------+
  503. | |RTL Partition |Replication |Instances |
  504. +-+--------------+------------+----------+
  505. +-+--------------+------------+----------+
  506. ---------------------------------------------------------------------------------
  507. Start IO Insertion
  508. ---------------------------------------------------------------------------------
  509. ---------------------------------------------------------------------------------
  510. Start Flattening Before IO Insertion
  511. ---------------------------------------------------------------------------------
  512. ---------------------------------------------------------------------------------
  513. Finished Flattening Before IO Insertion
  514. ---------------------------------------------------------------------------------
  515. ---------------------------------------------------------------------------------
  516. Start Final Netlist Cleanup
  517. ---------------------------------------------------------------------------------
  518. ---------------------------------------------------------------------------------
  519. Finished Final Netlist Cleanup
  520. ---------------------------------------------------------------------------------
  521. ---------------------------------------------------------------------------------
  522. Finished IO Insertion : Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1462.918 ; gain = 366.746 ; free physical = 235 ; free virtual = 10754
  523. ---------------------------------------------------------------------------------
  524.  
  525. Report Check Netlist:
  526. +------+------------------+-------+---------+-------+------------------+
  527. | |Item |Errors |Warnings |Status |Description |
  528. +------+------------------+-------+---------+-------+------------------+
  529. |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
  530. +------+------------------+-------+---------+-------+------------------+
  531. ---------------------------------------------------------------------------------
  532. Start Renaming Generated Instances
  533. ---------------------------------------------------------------------------------
  534. ---------------------------------------------------------------------------------
  535. Finished Renaming Generated Instances : Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1462.918 ; gain = 366.746 ; free physical = 235 ; free virtual = 10754
  536. ---------------------------------------------------------------------------------
  537.  
  538. Report RTL Partitions:
  539. +-+--------------+------------+----------+
  540. | |RTL Partition |Replication |Instances |
  541. +-+--------------+------------+----------+
  542. +-+--------------+------------+----------+
  543. ---------------------------------------------------------------------------------
  544. Start Rebuilding User Hierarchy
  545. ---------------------------------------------------------------------------------
  546. ---------------------------------------------------------------------------------
  547. Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1462.918 ; gain = 366.746 ; free physical = 235 ; free virtual = 10754
  548. ---------------------------------------------------------------------------------
  549. ---------------------------------------------------------------------------------
  550. Start Renaming Generated Ports
  551. ---------------------------------------------------------------------------------
  552. ---------------------------------------------------------------------------------
  553. Finished Renaming Generated Ports : Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1462.918 ; gain = 366.746 ; free physical = 235 ; free virtual = 10754
  554. ---------------------------------------------------------------------------------
  555. ---------------------------------------------------------------------------------
  556. Start Handling Custom Attributes
  557. ---------------------------------------------------------------------------------
  558. ---------------------------------------------------------------------------------
  559. Finished Handling Custom Attributes : Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1462.918 ; gain = 366.746 ; free physical = 235 ; free virtual = 10754
  560. ---------------------------------------------------------------------------------
  561. ---------------------------------------------------------------------------------
  562. Start Renaming Generated Nets
  563. ---------------------------------------------------------------------------------
  564. ---------------------------------------------------------------------------------
  565. Finished Renaming Generated Nets : Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1462.918 ; gain = 366.746 ; free physical = 235 ; free virtual = 10754
  566. ---------------------------------------------------------------------------------
  567. ---------------------------------------------------------------------------------
  568. Start Writing Synthesis Report
  569. ---------------------------------------------------------------------------------
  570.  
  571. Report BlackBoxes:
  572. +------+--------------+----------+
  573. | |BlackBox name |Instances |
  574. +------+--------------+----------+
  575. |1 |system | 1|
  576. +------+--------------+----------+
  577.  
  578. Report Cell Usage:
  579. +------+-------+------+
  580. | |Cell |Count |
  581. +------+-------+------+
  582. |1 |system | 1|
  583. +------+-------+------+
  584.  
  585. Report Instance Areas:
  586. +------+---------+-------+------+
  587. | |Instance |Module |Cells |
  588. +------+---------+-------+------+
  589. |1 |top | | 0|
  590. +------+---------+-------+------+
  591. ---------------------------------------------------------------------------------
  592. Finished Writing Synthesis Report : Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1462.918 ; gain = 366.746 ; free physical = 235 ; free virtual = 10754
  593. ---------------------------------------------------------------------------------
  594. Synthesis finished with 0 errors, 0 critical warnings and 1 warnings.
  595. Synthesis Optimization Runtime : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 1462.918 ; gain = 112.504 ; free physical = 294 ; free virtual = 10813
  596. Synthesis Optimization Complete : Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1462.926 ; gain = 366.746 ; free physical = 294 ; free virtual = 10813
  597. INFO: [Project 1-571] Translating synthesized netlist
  598. INFO: [Project 1-570] Preparing netlist for logic optimization
  599. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
  600. INFO: [Project 1-111] Unisim Transformation Summary:
  601. No Unisim elements were transformed.
  602.  
  603. 12 Infos, 90 Warnings, 0 Critical Warnings and 0 Errors encountered.
  604. synth_design completed successfully
  605. synth_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:22 . Memory (MB): peak = 1468.918 ; gain = 385.328 ; free physical = 269 ; free virtual = 10773
  606. INFO: [Common 17-1381] The checkpoint '/home/frank/parallella/oh/src/parallella/fpga/headless_e16_z7010/system.runs/synth_1/system_wrapper.dcp' has been generated.
  607. report_utilization: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.06 . Memory (MB): peak = 1468.922 ; gain = 0.000 ; free physical = 273 ; free virtual = 10773
  608. INFO: [Common 17-206] Exiting Vivado at Tue Aug 8 01:37:03 2017...
  609. [Tue Aug 8 01:37:06 2017] synth_1 finished
  610. wait_on_run: Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:32 . Memory (MB): peak = 1235.926 ; gain = 8.000 ; free physical = 747 ; free virtual = 11247
  611. ## open_run synth_1
  612. Design is defaulting to impl run constrset: constrs_1
  613. Design is defaulting to synth run part: xc7z010clg400-1
  614. INFO: [Project 1-479] Netlist was created with Vivado 2017.2
  615. INFO: [Device 21-403] Loading part xc7z010clg400-1
  616. INFO: [Project 1-570] Preparing netlist for logic optimization
  617. Parsing XDC File [/home/frank/parallella/oh/src/parallella/fpga/parallella_timing.xdc]
  618. WARNING: [Vivado 12-584] No ports matched 'rxi_lclk_p'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_timing.xdc:1]
  619. WARNING: [Vivado 12-2489] -period contains time 3.333333 which will be rounded to 3.333 to ensure it is an integer multiple of 1 picosecond [/home/frank/parallella/oh/src/parallella/fpga/parallella_timing.xdc:1]
  620. WARNING: [Vivado 12-2489] -waveform contains time 1.666667 which will be rounded to 1.667 to ensure it is an integer multiple of 1 picosecond [/home/frank/parallella/oh/src/parallella/fpga/parallella_timing.xdc:1]
  621. CRITICAL WARNING: [Vivado 12-4739] create_clock:No valid object(s) found for '-objects [get_ports rxi_lclk_p]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_timing.xdc:1]
  622. Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
  623. Finished Parsing XDC File [/home/frank/parallella/oh/src/parallella/fpga/parallella_timing.xdc]
  624. Parsing XDC File [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc]
  625. WARNING: [Vivado 12-584] No ports matched 'hdmi_*'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:11]
  626. CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:11]
  627. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
  628. WARNING: [Vivado 12-584] No ports matched 'hdmi_d[8]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:12]
  629. CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:12]
  630. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
  631. WARNING: [Vivado 12-584] No ports matched 'hdmi_d[9]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:13]
  632. CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:13]
  633. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
  634. WARNING: [Vivado 12-584] No ports matched 'hdmi_d[10]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:14]
  635. CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:14]
  636. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
  637. WARNING: [Vivado 12-584] No ports matched 'hdmi_d[11]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:15]
  638. CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:15]
  639. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
  640. WARNING: [Vivado 12-584] No ports matched 'hdmi_d[12]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:16]
  641. CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:16]
  642. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
  643. WARNING: [Vivado 12-584] No ports matched 'hdmi_d[13]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:17]
  644. CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:17]
  645. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
  646. WARNING: [Vivado 12-584] No ports matched 'hdmi_d[14]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:18]
  647. CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:18]
  648. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
  649. WARNING: [Vivado 12-584] No ports matched 'hdmi_d[15]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:19]
  650. CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:19]
  651. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
  652. WARNING: [Vivado 12-584] No ports matched 'hdmi_d[16]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:20]
  653. CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:20]
  654. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
  655. WARNING: [Vivado 12-584] No ports matched 'hdmi_d[17]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:21]
  656. CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:21]
  657. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
  658. WARNING: [Vivado 12-584] No ports matched 'hdmi_d[18]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:22]
  659. CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:22]
  660. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
  661. WARNING: [Vivado 12-584] No ports matched 'hdmi_d[19]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:23]
  662. CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:23]
  663. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
  664. WARNING: [Vivado 12-584] No ports matched 'hdmi_d[20]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:24]
  665. CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:24]
  666. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
  667. WARNING: [Vivado 12-584] No ports matched 'hdmi_d[21]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:25]
  668. CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:25]
  669. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
  670. WARNING: [Vivado 12-584] No ports matched 'hdmi_d[22]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:26]
  671. CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:26]
  672. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
  673. WARNING: [Vivado 12-584] No ports matched 'hdmi_d[23]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:27]
  674. CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:27]
  675. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
  676. WARNING: [Vivado 12-584] No ports matched 'hdmi_clk'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:28]
  677. CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:28]
  678. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
  679. WARNING: [Vivado 12-584] No ports matched 'hdmi_vsync'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:29]
  680. CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:29]
  681. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
  682. WARNING: [Vivado 12-584] No ports matched 'hdmi_hsync'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:30]
  683. CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:30]
  684. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
  685. WARNING: [Vivado 12-584] No ports matched 'hdmi_de'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:31]
  686. CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:31]
  687. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
  688. WARNING: [Vivado 12-584] No ports matched 'hdmi_spdif'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:32]
  689. CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:32]
  690. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
  691. WARNING: [Vivado 12-584] No ports matched 'hdmi_int'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:33]
  692. CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:33]
  693. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
  694. WARNING: [Vivado 12-584] No ports matched 'i2c_*'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:38]
  695. CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:38]
  696. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
  697. WARNING: [Vivado 12-584] No ports matched 'i2c_scl'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:39]
  698. CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:39]
  699. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
  700. WARNING: [Vivado 12-584] No ports matched 'i2c_sda'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:40]
  701. CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:40]
  702. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
  703. WARNING: [Vivado 12-584] No ports matched 'chip_nreset'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:45]
  704. CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:45]
  705. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
  706. WARNING: [Vivado 12-584] No ports matched 'chip_nreset'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:46]
  707. CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:46]
  708. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
  709. WARNING: [Vivado 12-584] No ports matched 'cclk*'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:51]
  710. CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:51]
  711. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
  712. WARNING: [Vivado 12-584] No ports matched 'cclk_n'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:52]
  713. CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:52]
  714. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
  715. WARNING: [Vivado 12-584] No ports matched 'txo*'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:57]
  716. CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:57]
  717. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
  718. WARNING: [Vivado 12-584] No ports matched 'txi*'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:58]
  719. CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:58]
  720. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
  721. WARNING: [Vivado 12-584] No ports matched 'txo_lclk_n'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:59]
  722. CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:59]
  723. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
  724. WARNING: [Vivado 12-584] No ports matched 'txo_data_n[0]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:60]
  725. CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:60]
  726. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
  727. WARNING: [Vivado 12-584] No ports matched 'txo_data_n[1]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:61]
  728. CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:61]
  729. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
  730. WARNING: [Vivado 12-584] No ports matched 'txo_data_n[2]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:62]
  731. CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:62]
  732. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
  733. WARNING: [Vivado 12-584] No ports matched 'txo_data_n[3]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:63]
  734. CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:63]
  735. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
  736. WARNING: [Vivado 12-584] No ports matched 'txo_data_n[4]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:64]
  737. CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:64]
  738. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
  739. WARNING: [Vivado 12-584] No ports matched 'txo_data_n[5]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:65]
  740. CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:65]
  741. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
  742. WARNING: [Vivado 12-584] No ports matched 'txo_data_n[6]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:66]
  743. CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:66]
  744. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
  745. WARNING: [Vivado 12-584] No ports matched 'txo_data_n[7]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:67]
  746. CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:67]
  747. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
  748. WARNING: [Vivado 12-584] No ports matched 'txo_frame_n'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:68]
  749. CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:68]
  750. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
  751. WARNING: [Vivado 12-584] No ports matched 'txi_wr_wait_n'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:69]
  752. CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:69]
  753. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
  754. WARNING: [Vivado 12-584] No ports matched 'txi_rd_wait_*'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:74]
  755. CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:74]
  756. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
  757. WARNING: [Vivado 12-584] No ports matched 'txi_rd_wait_p'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:75]
  758. CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:75]
  759. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
  760. WARNING: [Vivado 12-584] No ports matched 'rx*'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:81]
  761. CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:81]
  762. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
  763. WARNING: [Vivado 12-584] No ports matched 'rxi_lclk_n'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:82]
  764. CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:82]
  765. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
  766. WARNING: [Vivado 12-584] No ports matched 'rxi_data_n[0]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:83]
  767. CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:83]
  768. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
  769. WARNING: [Vivado 12-584] No ports matched 'rxi_data_n[1]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:84]
  770. CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:84]
  771. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
  772. WARNING: [Vivado 12-584] No ports matched 'rxi_data_n[2]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:85]
  773. CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:85]
  774. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
  775. WARNING: [Vivado 12-584] No ports matched 'rxi_data_n[3]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:86]
  776. CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:86]
  777. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
  778. WARNING: [Vivado 12-584] No ports matched 'rxi_data_n[4]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:87]
  779. CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:87]
  780. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
  781. WARNING: [Vivado 12-584] No ports matched 'rxi_data_n[5]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:88]
  782. CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:88]
  783. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
  784. WARNING: [Vivado 12-584] No ports matched 'rxi_data_n[6]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:89]
  785. CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:89]
  786. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
  787. WARNING: [Vivado 12-584] No ports matched 'rxi_data_n[7]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:90]
  788. CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:90]
  789. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
  790. WARNING: [Vivado 12-584] No ports matched 'rxi_frame_n'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:91]
  791. CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:91]
  792. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
  793. WARNING: [Vivado 12-584] No ports matched 'rxo_rd_wait_n'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:92]
  794. CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:92]
  795. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
  796. WARNING: [Vivado 12-584] No ports matched 'rxo_wr_wait_n'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:93]
  797. CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:93]
  798. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
  799. WARNING: [Vivado 12-584] No ports matched 'gpio*'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:99]
  800. CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:99]
  801. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
  802. WARNING: [Vivado 12-584] No ports matched 'gpio_p[0]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:100]
  803. CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:100]
  804. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
  805. WARNING: [Vivado 12-584] No ports matched 'gpio_n[0]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:101]
  806. CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:101]
  807. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
  808. WARNING: [Vivado 12-584] No ports matched 'gpio_p[1]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:102]
  809. CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:102]
  810. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
  811. WARNING: [Vivado 12-584] No ports matched 'gpio_n[1]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:103]
  812. CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:103]
  813. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
  814. WARNING: [Vivado 12-584] No ports matched 'gpio_p[2]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:104]
  815. CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:104]
  816. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
  817. WARNING: [Vivado 12-584] No ports matched 'gpio_n[2]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:105]
  818. CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:105]
  819. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
  820. WARNING: [Vivado 12-584] No ports matched 'gpio_p[3]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:106]
  821. CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:106]
  822. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
  823. WARNING: [Vivado 12-584] No ports matched 'gpio_n[3]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:107]
  824. CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:107]
  825. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
  826. WARNING: [Vivado 12-584] No ports matched 'gpio_p[4]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:108]
  827. CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:108]
  828. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
  829. WARNING: [Vivado 12-584] No ports matched 'gpio_n[4]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:109]
  830. CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:109]
  831. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
  832. WARNING: [Vivado 12-584] No ports matched 'gpio_p[5]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:110]
  833. CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:110]
  834. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
  835. WARNING: [Vivado 12-584] No ports matched 'gpio_n[5]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:111]
  836. CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:111]
  837. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
  838. WARNING: [Vivado 12-584] No ports matched 'gpio_p[6]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:112]
  839. CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:112]
  840. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
  841. WARNING: [Vivado 12-584] No ports matched 'gpio_n[6]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:113]
  842. CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:113]
  843. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
  844. WARNING: [Vivado 12-584] No ports matched 'gpio_p[7]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:114]
  845. CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:114]
  846. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
  847. WARNING: [Vivado 12-584] No ports matched 'gpio_n[7]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:115]
  848. CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:115]
  849. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
  850. WARNING: [Vivado 12-584] No ports matched 'gpio_p[8]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:116]
  851. CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:116]
  852. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
  853. WARNING: [Vivado 12-584] No ports matched 'gpio_n[8]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:117]
  854. CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:117]
  855. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
  856. WARNING: [Vivado 12-584] No ports matched 'gpio_p[9]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:118]
  857. CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:118]
  858. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
  859. WARNING: [Vivado 12-584] No ports matched 'gpio_n[9]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:119]
  860. CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:119]
  861. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
  862. WARNING: [Vivado 12-584] No ports matched 'gpio_p[10]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:120]
  863. CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:120]
  864. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
  865. WARNING: [Vivado 12-584] No ports matched 'gpio_n[10]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:121]
  866. CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:121]
  867. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
  868. WARNING: [Vivado 12-584] No ports matched 'gpio_p[11]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:122]
  869. CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:122]
  870. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
  871. WARNING: [Vivado 12-584] No ports matched 'gpio_n[11]'. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:123]
  872. CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc:123]
  873. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
  874. Finished Parsing XDC File [/home/frank/parallella/oh/src/parallella/fpga/parallella_io.xdc]
  875. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
  876. CRITICAL WARNING: [Project 1-486] Could not resolve non-primitive black box cell 'system' instantiated as 'system_i' [/home/frank/parallella/oh/src/parallella/fpga/headless_e16_z7010/system.srcs/sources_1/bd/system/hdl/system_wrapper.v:16]
  877. INFO: [Project 1-111] Unisim Transformation Summary:
  878. No Unisim elements were transformed.
  879.  
  880. ## report_timing_summary -file timing_synth.log
  881. INFO: [Timing 38-35] Done setting XDC timing constraints.
  882. INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
  883. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
  884. report_timing_summary: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 1890.043 ; gain = 457.523 ; free physical = 261 ; free virtual = 10675
  885. ## write_hwdef -force -file "${design}.hwdef"
  886. ## set_property STEPS.PHYS_OPT_DESIGN.IS_ENABLED true [get_runs impl_1]
  887. ## set_property STEPS.PHYS_OPT_DESIGN.ARGS.DIRECTIVE Explore [get_runs impl_1]
  888. ## set_property STRATEGY "Performance_Explore" [get_runs impl_1]
  889. ## launch_runs impl_1
  890. [Tue Aug 8 01:37:16 2017] Launched impl_1...
  891. Run output will be captured here: /home/frank/parallella/oh/src/parallella/fpga/headless_e16_z7010/system.runs/impl_1/runme.log
  892. ## wait_on_run impl_1
  893. [Tue Aug 8 01:37:16 2017] Waiting for impl_1 to finish...
  894.  
  895. *** Running vivado
  896. with args -log system_wrapper.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source system_wrapper.tcl -notrace
  897.  
  898.  
  899. ****** Vivado v2017.2 (64-bit)
  900. **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017
  901. **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017
  902. ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
  903.  
  904. source system_wrapper.tcl -notrace
  905. Command: open_checkpoint /home/frank/parallella/oh/src/parallella/fpga/headless_e16_z7010/system.runs/impl_1/system_wrapper.dcp
  906.  
  907. Starting open_checkpoint Task
  908.  
  909. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1081.574 ; gain = 0.000 ; free physical = 258 ; free virtual = 10560
  910. INFO: [Project 1-479] Netlist was created with Vivado 2017.2
  911. INFO: [Device 21-403] Loading part xc7z010clg400-1
  912. INFO: [Project 1-570] Preparing netlist for logic optimization
  913. Parsing XDC File [/home/frank/parallella/oh/src/parallella/fpga/headless_e16_z7010/system.runs/impl_1/.Xil/Vivado-8433-xps8900/dcp3/system_wrapper.xdc]
  914. Finished Parsing XDC File [/home/frank/parallella/oh/src/parallella/fpga/headless_e16_z7010/system.runs/impl_1/.Xil/Vivado-8433-xps8900/dcp3/system_wrapper.xdc]
  915. CRITICAL WARNING: [Project 1-486] Could not resolve non-primitive black box cell 'system' instantiated as 'system_i' [/home/frank/parallella/oh/src/parallella/fpga/headless_e16_z7010/system.srcs/sources_1/bd/system/hdl/system_wrapper.v:16]
  916. INFO: [Project 1-111] Unisim Transformation Summary:
  917. No Unisim elements were transformed.
  918.  
  919. INFO: [Project 1-604] Checkpoint was created with Vivado v2017.2 (64-bit) build 1909853
  920. Command: opt_design -directive Explore
  921. INFO: [Vivado_Tcl 4-136] Directive used for opt_design is: Explore
  922. Attempting to get a license for feature 'Implementation' and/or device 'xc7z010-clg400'
  923. INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010-clg400'
  924. Running DRC as a precondition to command opt_design
  925.  
  926. Starting DRC Task
  927. Command: report_drc (run_mandatory_drcs) for: opt_checks
  928. INFO: [DRC 23-27] Running DRC with 8 threads
  929. ERROR: [DRC INBB-3] Black Box Instances: Cell 'system_i' of type 'system_i/system' has undefined contents and is considered a black box. The contents of this cell must be defined for opt_design to complete successfully.
  930. report_drc (run_mandatory_drcs) completed successfully
  931. INFO: [Project 1-461] DRC finished with 1 Errors
  932. INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
  933. ERROR: [Vivado_Tcl 4-78] Error(s) found during DRC. Opt_design not run.
  934.  
  935. Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.24 . Memory (MB): peak = 1376.766 ; gain = 64.023 ; free physical = 231 ; free virtual = 10313
  936. 10 Infos, 0 Warnings, 1 Critical Warnings and 2 Errors encountered.
  937. opt_design failed
  938. ERROR: [Common 17-39] 'opt_design' failed due to earlier errors.
  939.  
  940. INFO: [Common 17-206] Exiting Vivado at Tue Aug 8 01:37:26 2017...
  941. [Tue Aug 8 01:37:28 2017] impl_1 finished
  942. wait_on_run: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:12 . Memory (MB): peak = 1914.059 ; gain = 0.000 ; free physical = 611 ; free virtual = 10693
  943. ## open_run impl_1
  944. ERROR: [Common 17-69] Command failed: Run 'impl_1' failed. Unable to open
  945.  
  946. while executing
  947. "source ../../../common/fpga/system_build.tcl"
  948. (file "run.tcl" line 12)
  949. INFO: [Common 17-206] Exiting Vivado at Tue Aug 8 01:37:28 2017...
  950. Makefile:24: recipe for target 'all' failed
  951. make[1]: *** [all] Error 1
  952. make[1]: Leaving directory '/home/frank/parallella/oh/src/parallella/fpga/headless_e16_z7010'
  953. Makefile:5: recipe for target 'all' failed
  954. make: *** [all] Error 2
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