`timescale 1ns / 1ps
module rategen_1(
    input clk,
    output cy1
    );
reg [25:0] q = 0;
always @(posedge clk)
    if(~cy1)
        q <= q+1;
    else q <= 0;
//assign cy = (q == 49999999);
assign cy1 = (q == 4); //for testing purpose
endmodule

////////////////////////////////////////////////

`timescale 1ns / 1ps
module rategen_2(
    input clk,
    output cy2
    );
reg [25:0] q = 0;
always @(posedge clk)
    if(~cy2)
        q <= q+2;
    else q <= 0;
//assign cy = (q == 49999999);
assign cy2 = (q == 4); //for testing purpose
endmodule

///////////////////////////////////////////////

`timescale 1ns / 1ps
module melyik(
    input clk,
    input dir,
     input ce1,ce2,
    output led
    );
reg ld;
always @(posedge clk)
    if(dir==1)
        ld <= (~ce2);
    else
        ld <= ce1;
assign led=ld;
endmodule