#include "qemu/osdep.h"
#include "qemu/units.h"
#include "qemu/cutils.h"
#include "qapi/error.h"
#include "qemu/error-report.h"
#include "hw/arm/boot.h"
#include "hw/arm/armv7m.h"
#include "hw/or-irq.h"
#include "hw/boards.h"
#include "exec/address-spaces.h"
#include "sysemu/sysemu.h"
#include "hw/qdev-properties.h"
#include "hw/misc/unimp.h"
#include "hw/char/cmsdk-apb-uart.h"
#include "hw/timer/cmsdk-apb-timer.h"
#include "hw/timer/cmsdk-apb-dualtimer.h"
#include "hw/misc/mps2-scc.h"
#include "hw/misc/mps2-fpgaio.h"
#include "hw/ssi/pl022.h"
#include "hw/i2c/arm_sbcon_i2c.h"
#include "hw/net/lan9118.h"
#include "net/net.h"
#include "hw/watchdog/cmsdk-apb-watchdog.h"
#include "hw/qdev-clock.h"
#include "qom/object.h"


#define TYPE_STM32WB5MMGH6TR_MACHINE MACHINE_TYPE_NAME("stm32wb5mmgh6tr")
#define STM32WB5MMGH6TR_MACHINE(obj) \
    OBJECT_CHECK(STM32WB5MMGH6TRMachineState, (obj), TYPE_STM32WB5MMGH6TR_MACHINE)

/* Main SYSCLK frequency in Hz */
#define SYSCLK_FRQ 25000000
#define REFCLK_FRQ (1 * 1000 * 1000)

#define FLASH_BASE_ADDR 0x08000000
#define FLASH_SIZE (1 * MiB)

#define SRAM1_BASE_ADDR 0x20000000
#define SRAM1_SIZE (256 * KiB)

#define SRAM2_BASE_ADDR 0x10000000
#define SRAM2_SIZE (128 * KiB)

typedef struct STM32WB5MMGH6TRMachineState {
    MachineState parent;
    ARMv7MState armv7m;
    MemoryRegion flash;
    MemoryRegion sram1;
    MemoryRegion sram2;
    Clock *sysclk;
    Clock *refclk;
} STM32WB5MMGH6TRMachineState;

static void stm32wb5mmgh6tr_init(MachineState *machine)
{
    STM32WB5MMGH6TRMachineState *sms = STM32WB5MMGH6TR_MACHINE(machine);
    MachineClass *mc = MACHINE_GET_CLASS(machine);
    DeviceState *armv7m;

    /* This clock doesn't need migration because it is fixed-frequency */
    sms->sysclk = clock_new(OBJECT(machine), "SYSCLK");
    clock_set_hz(sms->sysclk, SYSCLK_FRQ);

    sms->refclk = clock_new(OBJECT(machine), "REFCLK");
    clock_set_hz(sms->refclk, REFCLK_FRQ);

    // Initialization code here...
    object_initialize_child(OBJECT(sms), "armv7m", &sms->armv7m, TYPE_ARMV7M);
    armv7m = DEVICE(&sms->armv7m);

    qdev_connect_clock_in(armv7m, "cpuclk", sms->sysclk);
    qdev_connect_clock_in(armv7m, "refclk", sms->refclk);
    qdev_prop_set_string(armv7m, "cpu-type", mc->default_cpu_type);
    object_property_set_link(OBJECT(&sms->armv7m), "memory",
                             OBJECT(get_system_memory()), &error_abort);
    sysbus_realize(SYS_BUS_DEVICE(&sms->armv7m), &error_fatal);

    // Initialize Flash
    memory_region_init_ram(&sms->flash, OBJECT(machine), "stm32wb5mmgh6tr.flash", FLASH_SIZE, &error_fatal);
    memory_region_add_subregion(get_system_memory(), FLASH_BASE_ADDR, &sms->flash);

    // Initialize SRAM1
    memory_region_init_ram(&sms->sram1, OBJECT(machine), "stm32wb5mmgh6tr.sram1", SRAM1_SIZE, &error_fatal);
    memory_region_add_subregion(get_system_memory(), SRAM1_BASE_ADDR, &sms->sram1);

    // Initialize SRAM2
    memory_region_init_ram(&sms->sram2, OBJECT(machine), "stm32wb5mmgh6tr.sram2", SRAM2_SIZE, &error_fatal);
    memory_region_add_subregion(get_system_memory(), SRAM2_BASE_ADDR, &sms->sram2);


    // Load kernel
//    armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,
//                       0x20000000, 512 * 1024);  // Adjust these values as per STM32WB5MMGH6TR specs
}

static void stm32wb5mmgh6tr_class_init(ObjectClass *oc, void *data)
{
    MachineClass *mc = MACHINE_CLASS(oc);

    mc->desc = "STM32WB5MMGH6TR Board";
    mc->init = stm32wb5mmgh6tr_init;
    mc->max_cpus = 1;
    mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m4");
}

static const TypeInfo stm32wb5mmgh6tr_machine_info = {
        .name = TYPE_STM32WB5MMGH6TR_MACHINE,
        .parent = TYPE_MACHINE,
        .instance_size = sizeof(STM32WB5MMGH6TRMachineState),
        .class_init = stm32wb5mmgh6tr_class_init,
};

static void stm32wb5mmgh6tr_machine_init(void)
{
    type_register_static(&stm32wb5mmgh6tr_machine_info);
}

type_init(stm32wb5mmgh6tr_machine_init);