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Oct 31st, 2018
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ARM 5.04 KB | None | 0 0
  1.     PRESERVE8
  2.     AREA MyCode,CODE,READONLY
  3.     EXPORT config
  4.     IMPORT my_fprint
  5.     EXPORT asm_pit1_irq
  6. PIT1_IRQHandler EQU asm_pit1_irq+1
  7.     EXPORT PIT1_IRQHandler      ;the vector table must contain odd addresses for the Cortex processor
  8. my_SIM_SCGC5 EQU    0x40048038      ;Address for SIM_SCGC5
  9. my_GPIOC_clken EQU  0x00000800      ;Clock gate enable for port A
  10. my_PORTC_PCR0 EQU   0x4004B000
  11. PORTC_PCR_VAL EQU   0x00000140
  12. ;my_GPIOA_PDOR EQU  0x400FF000
  13. my_GPIOC_PDDR EQU   0x400FF094
  14. my_GPIOC_PDOR EQU   0x400FF080
  15. my_GPIOC_PCOR EQU   0x400FF088
  16. my_GPIOC_PSOR EQU   0x400FF084
  17. ;GPIOA_PDOR_VAL EQU 0x30000800
  18. GPIOC_PDDR_VAL EQU  0x000007FF
  19. ;my_GPIOA_PCOR EQU  0x400FF008
  20. ;my_GPIOA_PSOR EQU  0x400FF004
  21. my_SIM_SCGC6 EQU    0x4004803C
  22. my_SCGC6_value EQU  0x00800000
  23.    
  24. my_PIT_MCR EQU      0x40037000
  25. my_PIT_LDVAL1 EQU   0x40037110
  26. my_LDVAL1_value EQU 0x0000C34F
  27. my_PIT_TFLG1 EQU    0x4003711C
  28. my_PIT_TCTRL1 EQU   0x40037118
  29.    
  30. my_NVIC_addr EQU    0xE000E108
  31. my_NVIC_value EQU   0x00000020
  32. config
  33.  
  34. ;write 1 to bit {11} of SIM_SCGC5, enable Port C clock gate
  35.     LDR     r2, =my_SIM_SCGC5       ;0x40048038
  36.     LDR     r1, =my_GPIOC_clken     ;0x00000800
  37.     LDR     r3, [r2]
  38.     ORR     r3, r3, r1
  39.     STR     r3, [r2]                ;enable GPIO_PORTC
  40.  
  41. ;For PortC PCR0-PCR10:
  42. ;write 1 to bit {6}, DSE, high drive strength
  43. ;write 001 to bits {8-10}, MUX, alternative 1 GPIO
  44.     MOV     r4, #0
  45.     LDR     r2, =my_PORTC_PCR0      ;0x4004B000 address PortC PCR0
  46.     LDR     r1, =PORTC_PCR_VAL      ;0x00000140
  47. next_portc
  48.     STR r1,[r2], #4
  49.     ADD r4,r4,#1
  50.     CMP r4,#11
  51.     BNE next_portc
  52.    
  53. ;set PDDR PCR bits 0-10 to logic 1 - set them as outputs
  54. ;bits 0-10 set to 1 (= 0x07ff)
  55.     LDR     r2, =my_GPIOC_PDDR      ;0x4000FF094
  56.     LDR     r1, =GPIOC_PDDR_VAL     ;0x0000007FF
  57.     STR     r1, [r2]
  58.    
  59. ;initializing off at reset
  60.     LDR r2, =my_GPIOC_PDOR
  61.     LDR r5, =0x000000FF
  62.     STR r5,[r2]
  63.    
  64. ;Set PIT timer by writing 1 to bit {23} of SIM_SCGC6
  65.     LDR      r2,=my_SIM_SCGC6       ;0x4004803C
  66.     LDR      r1,=my_SCGC6_value     ;0x00800000
  67.     LDR      r0,[r2]
  68.     ORR      r0,r0,r1
  69.     STR      r0,[r2]                ;enable clock to PIT1
  70.  
  71. ;enable the PIT module (0 to bits {0-1} of the MCR)
  72.     LDR      r2,=my_PIT_MCR         ;0x40037000, memory address for PCR
  73.     MOV      r0,#0
  74.     STR      r0,[r2]                ;stores 0x0 into PCR
  75.    
  76. ;sets the timer to interrupt every 2s by writing LDVAL1
  77.     LDR      r2,=my_PIT_LDVAL1      ;0x40037110, memory address for PIT_LDVAL1
  78. ;want it to trigger every 2s
  79. ;1ms/20ns - 1 =50e3 - 1 =0xC34F
  80.     LDR      r1,=my_LDVAL1_value    ;0xC34F
  81.     STR      r1,[r2]                ;load the count value to generate interrupt periodically
  82.  
  83. ;store 1 in bits {0,1} of TCTRL1, enable timer and interrupts
  84.     LDR      r2,=my_PIT_TCTRL1      ;0x40037118, memory address for PIT_TCTRL1
  85.     MOV      r0,#0x3
  86.     STR      r0,[r2]                ;set TIE and TEN bits
  87.  
  88. ;NVIC CONVIG
  89.     LDR      r2,=my_NVIC_value      ;0x00000020 sets IRQ 69
  90.     LDR      r1,=my_NVIC_addr       ;0xE000E108
  91.     STR      r2, [r1]
  92.    
  93.    
  94.     LDR      r5, =value             ;loads address of value for 7seg
  95.    
  96.    
  97. loop B loop
  98.    
  99. asm_pit1_irq
  100.     PUSH     {lr}                   ;store LR
  101.     LDR      r2,=my_PIT_TFLG1       ;load memory address of TFLG1
  102.     MOV      r3,#0x01               ;1 to clear flag
  103.     STR      r3,[r2]                ;store 1 to the memory to clear flags
  104.     LDR      r2, =irqcounter        ;load memory address of counter
  105.     LDRB     r3,[r2]                ;loads value from counter into r3
  106.     B        sevSeg
  107.  
  108. sevSeg
  109.     LDR      r7, =sevSegTable       ;loads address of lookup table
  110.     LDR      r6, [r5], #4           ;loads first value to be printed
  111.     LSL      r6, r6, #2             ;multiply value by 4
  112.     ADD      r6, r6, r7             ;add shift value to memory address
  113.     LDR      r8, [r6]               ;load value from lookup table
  114.     LDR      R9, =my_GPIOC_PDOR     ;load PDOR address to output
  115.     CMP      r3, #1                 ;branch to correct digit #
  116.     BEQ      dig_one
  117.     BGT      dig_two
  118.    
  119. dig_zero
  120.     ADD      r3,#1                  ;increment counter 
  121.     STRB     r3,[r2]                ;updating counter in memory
  122.     add      r8, r8, #0x400         ;0x400 turns on MS digit PTC10
  123.     ldr      r11, [r5]              ;check if next value is period
  124.     cmp      r11, #0x2E             ;print to 7seg and update address if true
  125.     subeq    r8, r8, #0x80
  126.     addeq    r5, r5, #4
  127.     str      r8, [r9]               ;store value in PDOR
  128.     pop      {pc}                   ;restore program
  129.    
  130. dig_one
  131.     ADD      r3,#1                  ;increment counter 
  132.     STRB     r3,[r2]                ;updating counter in memory
  133.     add      r8, r8, #0x200         ;0x200 turns on middle digit PTC9
  134.     ldr      r11, [r5]              ;check if next value is period
  135.     cmp      r11, #0x2E             ;print to 7seg and update address if true
  136.     subeq    r8, r8, #0x80
  137.     addeq    r5, r5, #4
  138.     str      r8, [r9]               ;store value in PDOR
  139.     POP      {pc}                   ;restore program
  140. dig_two
  141.     mov      r3, #0x0               ;reset counter (limit between 0 and 2)
  142.     strb     r3, [r2]               ;store 0 in counter memory
  143.     add      r8, r8, #0x100         ;0x100 turns on LS digit PTC8
  144.     ldr      r11, [r5]              ;check if next value is period
  145.     cmp      r11, #0x2E             ;print to 7seg and update address if true
  146.     subeq    r8, r8, #0x80
  147.     addeq    r5, r5, #4
  148.     STR      r8, [r9]               ;store value in PDOR
  149.     LDR      r5, =value             ;restart from first digit
  150.     POP      {pc}                   ;restore program
  151.    
  152.    
  153.     ALIGN
  154.     AREA MyData, DATA, READWRITE
  155. irqcounter  DCD 0x00
  156. value       DCD 0x07
  157.             dcd 0x2E
  158.             DCD 0x01
  159.             DCD 0x2E
  160.             DCD 0x02
  161.             dcd 0x2e
  162. sevSegTable DCD 0xC0
  163.             DCD 0xF9
  164.             DCD 0xA4
  165.             DCD 0xB0
  166.             DCD 0x99
  167.             DCD 0x92
  168.             DCD 0x82
  169.             DCD 0xF8
  170.             DCD 0x98
  171.             DCD 0xFF    ;period
  172.                
  173.            
  174.        
  175. DCD
  176.  
  177.     END
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