Advertisement
Not a member of Pastebin yet?
Sign Up,
it unlocks many cool features!
- PRESERVE8
- AREA MyCode,CODE,READONLY
- EXPORT config
- IMPORT my_fprint
- EXPORT asm_pit1_irq
- PIT1_IRQHandler EQU asm_pit1_irq+1
- EXPORT PIT1_IRQHandler ;the vector table must contain odd addresses for the Cortex processor
- my_SIM_SCGC5 EQU 0x40048038 ;Address for SIM_SCGC5
- my_GPIOC_clken EQU 0x00000800 ;Clock gate enable for port A
- my_PORTC_PCR0 EQU 0x4004B000
- PORTC_PCR_VAL EQU 0x00000140
- ;my_GPIOA_PDOR EQU 0x400FF000
- my_GPIOC_PDDR EQU 0x400FF094
- my_GPIOC_PDOR EQU 0x400FF080
- my_GPIOC_PCOR EQU 0x400FF088
- my_GPIOC_PSOR EQU 0x400FF084
- ;GPIOA_PDOR_VAL EQU 0x30000800
- GPIOC_PDDR_VAL EQU 0x000007FF
- ;my_GPIOA_PCOR EQU 0x400FF008
- ;my_GPIOA_PSOR EQU 0x400FF004
- my_SIM_SCGC6 EQU 0x4004803C
- my_SCGC6_value EQU 0x00800000
- my_PIT_MCR EQU 0x40037000
- my_PIT_LDVAL1 EQU 0x40037110
- my_LDVAL1_value EQU 0x0000C34F
- my_PIT_TFLG1 EQU 0x4003711C
- my_PIT_TCTRL1 EQU 0x40037118
- my_NVIC_addr EQU 0xE000E108
- my_NVIC_value EQU 0x00000020
- config
- ;write 1 to bit {11} of SIM_SCGC5, enable Port C clock gate
- LDR r2, =my_SIM_SCGC5 ;0x40048038
- LDR r1, =my_GPIOC_clken ;0x00000800
- LDR r3, [r2]
- ORR r3, r3, r1
- STR r3, [r2] ;enable GPIO_PORTC
- ;For PortC PCR0-PCR10:
- ;write 1 to bit {6}, DSE, high drive strength
- ;write 001 to bits {8-10}, MUX, alternative 1 GPIO
- MOV r4, #0
- LDR r2, =my_PORTC_PCR0 ;0x4004B000 address PortC PCR0
- LDR r1, =PORTC_PCR_VAL ;0x00000140
- next_portc
- STR r1,[r2], #4
- ADD r4,r4,#1
- CMP r4,#11
- BNE next_portc
- ;set PDDR PCR bits 0-10 to logic 1 - set them as outputs
- ;bits 0-10 set to 1 (= 0x07ff)
- LDR r2, =my_GPIOC_PDDR ;0x4000FF094
- LDR r1, =GPIOC_PDDR_VAL ;0x0000007FF
- STR r1, [r2]
- ;initializing off at reset
- LDR r2, =my_GPIOC_PDOR
- LDR r5, =0x000000FF
- STR r5,[r2]
- ;Set PIT timer by writing 1 to bit {23} of SIM_SCGC6
- LDR r2,=my_SIM_SCGC6 ;0x4004803C
- LDR r1,=my_SCGC6_value ;0x00800000
- LDR r0,[r2]
- ORR r0,r0,r1
- STR r0,[r2] ;enable clock to PIT1
- ;enable the PIT module (0 to bits {0-1} of the MCR)
- LDR r2,=my_PIT_MCR ;0x40037000, memory address for PCR
- MOV r0,#0
- STR r0,[r2] ;stores 0x0 into PCR
- ;sets the timer to interrupt every 2s by writing LDVAL1
- LDR r2,=my_PIT_LDVAL1 ;0x40037110, memory address for PIT_LDVAL1
- ;want it to trigger every 2s
- ;1ms/20ns - 1 =50e3 - 1 =0xC34F
- LDR r1,=my_LDVAL1_value ;0xC34F
- STR r1,[r2] ;load the count value to generate interrupt periodically
- ;store 1 in bits {0,1} of TCTRL1, enable timer and interrupts
- LDR r2,=my_PIT_TCTRL1 ;0x40037118, memory address for PIT_TCTRL1
- MOV r0,#0x3
- STR r0,[r2] ;set TIE and TEN bits
- ;NVIC CONVIG
- LDR r2,=my_NVIC_value ;0x00000020 sets IRQ 69
- LDR r1,=my_NVIC_addr ;0xE000E108
- STR r2, [r1]
- LDR r5, =value ;loads address of value for 7seg
- loop B loop
- asm_pit1_irq
- PUSH {lr} ;store LR
- LDR r2,=my_PIT_TFLG1 ;load memory address of TFLG1
- MOV r3,#0x01 ;1 to clear flag
- STR r3,[r2] ;store 1 to the memory to clear flags
- LDR r2, =irqcounter ;load memory address of counter
- LDRB r3,[r2] ;loads value from counter into r3
- B sevSeg
- sevSeg
- LDR r7, =sevSegTable ;loads address of lookup table
- LDR r6, [r5], #4 ;loads first value to be printed
- LSL r6, r6, #2 ;multiply value by 4
- ADD r6, r6, r7 ;add shift value to memory address
- LDR r8, [r6] ;load value from lookup table
- LDR R9, =my_GPIOC_PDOR ;load PDOR address to output
- CMP r3, #1 ;branch to correct digit #
- BEQ dig_one
- BGT dig_two
- dig_zero
- ADD r3,#1 ;increment counter
- STRB r3,[r2] ;updating counter in memory
- add r8, r8, #0x400 ;0x400 turns on MS digit PTC10
- ldr r11, [r5] ;check if next value is period
- cmp r11, #0x2E ;print to 7seg and update address if true
- subeq r8, r8, #0x80
- addeq r5, r5, #4
- str r8, [r9] ;store value in PDOR
- pop {pc} ;restore program
- dig_one
- ADD r3,#1 ;increment counter
- STRB r3,[r2] ;updating counter in memory
- add r8, r8, #0x200 ;0x200 turns on middle digit PTC9
- ldr r11, [r5] ;check if next value is period
- cmp r11, #0x2E ;print to 7seg and update address if true
- subeq r8, r8, #0x80
- addeq r5, r5, #4
- str r8, [r9] ;store value in PDOR
- POP {pc} ;restore program
- dig_two
- mov r3, #0x0 ;reset counter (limit between 0 and 2)
- strb r3, [r2] ;store 0 in counter memory
- add r8, r8, #0x100 ;0x100 turns on LS digit PTC8
- ldr r11, [r5] ;check if next value is period
- cmp r11, #0x2E ;print to 7seg and update address if true
- subeq r8, r8, #0x80
- addeq r5, r5, #4
- STR r8, [r9] ;store value in PDOR
- LDR r5, =value ;restart from first digit
- POP {pc} ;restore program
- ALIGN
- AREA MyData, DATA, READWRITE
- irqcounter DCD 0x00
- value DCD 0x07
- dcd 0x2E
- DCD 0x01
- DCD 0x2E
- DCD 0x02
- dcd 0x2e
- sevSegTable DCD 0xC0
- DCD 0xF9
- DCD 0xA4
- DCD 0xB0
- DCD 0x99
- DCD 0x92
- DCD 0x82
- DCD 0xF8
- DCD 0x98
- DCD 0xFF ;period
- DCD
- END
Advertisement
Add Comment
Please, Sign In to add comment
Advertisement