// ----------------------------------------------------------------------------
//    File name: srt.v
//    Designed by: Jim Moran
// ----------------------------------------------------------------------------
//
//    The Synchronous Receiver Transmitter (SRT) provides a receive and a
//  transmit path between a full duplex serial synchronous transmission path
//  and an  eight bit processor interface.
//
// ----------------------------------------------------------------------------

`timescale 1ns/1ps

//-----------------------------------------------------------------------------
// Module Declaration
//-----------------------------------------------------------------------------
module srt (
        // Global Signals
        srt_clk_in,     // Clock Input
        srt_rst_l_in,   // Active Low Reset Input
        // Bus Interface
        srt_en_l_in,    // Active Low Bus Enable Input
        srt_wr_l_in,    // Active Low Bus Write Input
        srt_rd_l_in,    // Active Low Bus Read Input
        srt_addr_in,    // Address Input
        srt_data_inout, // Bidirectional Data Bus
            // Serial Interface
        srt_ser_in,     // Serial Data Input
        srt_ser_out     // Serial Data Output
        );

   //-----------------------------------------------------------------------------
   // IO Declarations
   //-----------------------------------------------------------------------------
   // Global Signals
   input       srt_clk_in;     // Clock Input
   input       srt_rst_l_in;   // Active Low Reset Input
   // Bus Interface
   input       srt_en_l_in;    // Active Low Bus Enable Input
   input       srt_wr_l_in;    // Active Low Bus Enable Input
   input       srt_rd_l_in;    // Active Low Bus Enable Input
   input [4:0] srt_addr_in;    // Address Input
   inout [7:0] srt_data_inout; // Bidirectional Data Bus
   // Serial Interface
   input       srt_ser_in;     // Serial Data Input
   output      srt_ser_out;     // Serial Data Output

   //-----------------------------------------------------------------------------
   // Output Registers
   //-----------------------------------------------------------------------------
   wire        srt_ser_out;  // Serial Data Register

   //-----------------------------------------------------------------------------
   // Parameters
   //-----------------------------------------------------------------------------
   parameter [7:0] SRT_IDLE = 8'b01111110;
   parameter [7:0] SRT_SYNC = 8'b10000001;

   //-----------------------------------------------------------------------------
   // Internal Registers and Wires
   //-----------------------------------------------------------------------------
   // Transmit Interface
   wire [7:0]  srt_txm_data;
   wire [2:0]  srt_txm_addr;
   wire        srt_txm_start;
   wire        srt_txm_done;
   // Receiver Interface
   wire [7:0]  srt_rxm_data;
   wire [2:0]  srt_rxm_addr;
   wire        srt_rxm_wr;
   wire        srt_rxm_error;
   wire        srt_rxm_done;

   //-----------------------------------------------------------------------------
   // Assigns
   //-----------------------------------------------------------------------------

   //-----------------------------------------------------------------------------
   // Instantiations
   //-----------------------------------------------------------------------------
   txm #(.TXM_IDLE (SRT_IDLE),
     .TXM_SYNC (SRT_SYNC))
   txm0(
    // Global Signals
    .txm_clk_in (srt_clk_in),        // Clock Input
    .txm_rst_l_in (srt_rst_l_in),    // Active Low Reset Input
    // Transmit Interface
    .txm_data_in (srt_txm_data),     // Data to transmitter Input
    .txm_addr_out (srt_txm_addr),     // Address for tramsitted data Output
    .txm_start_in (srt_txm_start),   // Transmit start Input
    .txm_done_out (srt_txm_done),    // Transmit done Output
        // Serial Interface
    .txm_ser_out(srt_ser_out)        // Serial Data Output
        );

   rxm #(.RXM_IDLE (SRT_IDLE),
     .RXM_SYNC (SRT_SYNC))
   rxm0(
    .rxm_clk_in (srt_clk_in),        // Clock Input
    .rxm_rst_l_in (srt_rst_l_in),    // Active Low Reset Input
    // Receive Interface
    .rxm_data_out (srt_rxm_data),    // Data to transmitter Output
    .rxm_addr_out (srt_rxm_addr),    // Address for tramsitted data Output
    .rxm_wr_out   (srt_rxm_wr),      // Write data enable Output
    .rxm_error_out (srt_rxm_error),  // Checksum error Output
    .rxm_done_out (srt_rxm_done),     // Receive done Output
        // Serial Interface
    .rxm_ser_in(srt_ser_in)          // Serial Data Input
        );

   bus bus0(
        // Global Signals
        .bus_clk_in (srt_clk_in),           // Clock Input
        .bus_rst_l_in (srt_rst_l_in),       // Active Low Reset Input
            // Bus Interface
        .bus_en_l_in (srt_en_l_in),         // Active Low Bus Enable Input
        .bus_wr_l_in (srt_wr_l_in),         // Active Low Bus Write Input
        .bus_rd_l_in (srt_rd_l_in),        // Active Low Bus Read Input
        .bus_addr_in (srt_addr_in),         // Addrress Input
        .bus_data_inout (srt_data_inout),   // Bidirectional Data Bus Inout
        // Receive Interface
        .bus_rxm_data_in (srt_rxm_data),    // Data from recveived Input
        .bus_rxm_addr_in (srt_rxm_addr),    // Address for received data Input
        .bus_rxm_wr_in (srt_rxm_wr),        // Write data enable Input
        .bus_rxm_error_in (srt_rxm_error),  // Checksum error Input
        .bus_rxm_done_in (srt_rxm_done),    // Receiver done Input
        // Transmit Interface
        .bus_txm_data_out (srt_txm_data),   // Data to transmitter Output
        .bus_txm_addr_in (srt_txm_addr),    // Address for tramsitted data Input
        .bus_txm_start_out (srt_txm_start), // Transmit start Output
        .bus_txm_done_in (srt_txm_done)     // Transmit done Input
        );

   //-----------------------------------------------------------------------------
   // RTL
   //-----------------------------------------------------------------------------

endmodule // srt